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X-CSE-ConnectionGUID: G10SpBRmSQmkijmnpGEBsQ== X-CSE-MsgGUID: eH2ozryURKekqjsd5XorIQ== X-IronPort-AV: E=McAfee;i="6800,10657,11498"; a="65999255" X-IronPort-AV: E=Sophos;i="6.16,328,1744095600"; d="scan'208";a="65999255" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2025 04:34:34 -0700 X-CSE-ConnectionGUID: s1G6XQ7ES76w4cqFCZDU9Q== X-CSE-MsgGUID: Se2oBYjySmuR/r3Ll5F1ow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,328,1744095600"; d="scan'208";a="162855980" Received: from smile.fi.intel.com ([10.237.72.52]) by fmviesa003.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2025 04:34:29 -0700 Received: from andy by smile.fi.intel.com with local (Exim 4.98.2) (envelope-from ) id 1udomn-0000000HKIR-3Rcd; Mon, 21 Jul 2025 14:34:25 +0300 Date: Mon, 21 Jul 2025 14:34:25 +0300 From: Andy Shevchenko To: AngeloGioacchino Del Regno Cc: sboyd@kernel.org, jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, srini@kernel.org, vkoul@kernel.org, kishon@kernel.org, sre@kernel.org, krzysztof.kozlowski@linaro.org, u.kleine-koenig@baylibre.com, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, wenst@chromium.org Subject: Re: [PATCH v1 1/7] spmi: Implement spmi_subdevice_alloc_and_add() and devm variant Message-ID: References: <20250721075525.29636-1-angelogioacchino.delregno@collabora.com> <20250721075525.29636-2-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250721075525.29636-2-angelogioacchino.delregno@collabora.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Mon, Jul 21, 2025 at 09:55:19AM +0200, AngeloGioacchino Del Regno wrote: > Some devices connected over the SPMI bus may be big, in the sense > that those may be a complex of devices managed by a single chip > over the SPMI bus, reachable through a single SID. > > Add new functions aimed at managing sub-devices of a SPMI device > spmi_subdevice_alloc_and_add() and a spmi_subdevice_put_and_remove() > for adding a new subdevice and removing it respectively, and also > add their devm_* variants. > > The need for such functions comes from the existance of those > complex Power Management ICs (PMICs), which feature one or many > sub-devices, in some cases with these being even addressable on > the chip in form of SPMI register ranges. > > Examples of those devices can be found in both Qualcomm platforms > with their PMICs having PON, RTC, SDAM, GPIO controller, and other > sub-devices, and in newer MediaTek platforms showing similar HW > features and a similar layout with those also having many subdevs. ... > EXPORT_SYMBOL_GPL(devm_spmi_controller_add); > +EXPORT_SYMBOL_GPL(devm_spmi_subdevice_alloc_and_add); I am wondering how hard to move these to a dedicated namespace. Basically you can define a default namespace, and at the same time add import to all (current) users. ... > + dev_set_name(&sdev->dev, > + "%d-%02x.%d.auto", sdev->ctrl->nr, sdev->usid, sub_sdev->devid); No error check? -- With Best Regards, Andy Shevchenko