From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 833C42BFC60 for ; Mon, 21 Jul 2025 14:54:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753109656; cv=none; b=ZMac+Vj52gM4qgJRVt5YTEBs1chwnRVTJsyiBlZgwLu6zVrQ3kS1H3tJCa5ITdBN7G34BbFUgkk+dxiw+4rP/NMx6/7rInREQrgzYYNzX2SpJCCmkva6VHEbpLMJnM+WC0GI6fFhSUeL1Md5b8pXSyGqbmL0yDUc1OwcK5WMIl0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753109656; c=relaxed/simple; bh=TnIn2jU1jHCRkCzr6cNbxSuwmFm4CVFn/2PAIWS1m40=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=nxy5umhVnjWiFQ6VnJrCraRCKMuruKTOfTpqr8Uq6EoZd5qbL1CysAVBxGuggfB94jeUkwIzBT3M7oJpmLxq3Qn1XDItuOFritvKNxTTfK1EsZCRqoPlefResArNZYLjN2ddD143EYoq7LoFiQFs7vUwL8YSqtcidqpWOzVd448= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 186DC153B for ; Mon, 21 Jul 2025 07:54:08 -0700 (PDT) Received: from e110455-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A5D663F6A8 for ; Mon, 21 Jul 2025 07:54:13 -0700 (PDT) Date: Mon, 21 Jul 2025 15:54:03 +0100 From: Liviu Dudau To: Karunika Choo Cc: dri-devel@lists.freedesktop.org, nd@arm.com, Boris Brezillon , Steven Price , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 5/6] drm/panthor: Make MMU cache maintenance use FLUSH_CACHES command Message-ID: References: <20250721111344.1610250-1-karunika.choo@arm.com> <20250721111344.1610250-6-karunika.choo@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250721111344.1610250-6-karunika.choo@arm.com> On Mon, Jul 21, 2025 at 12:13:43PM +0100, Karunika Choo wrote: > As the FLUSH_MEM and FLUSH_PT MMU_AS commands are deprecated in GPUs > from Mali-Gx20 onwards, this patch adds support for performing cache > maintenance via the FLUSH_CACHES command in GPU_COMMAND in place of > FLUSH_MEM and FLUSH_PT commands. > > Mali-Gx10 and Mali-Gx15 GPUs also has support for the FLUSH_CACHES > command and will also use this by default going forward. > > Signed-off-by: Karunika Choo Reviewed-by: Liviu Dudau Best regards, Liviu > --- > drivers/gpu/drm/panthor/panthor_mmu.c | 33 +++++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c b/drivers/gpu/drm/panthor/panthor_mmu.c > index 4140f697ba5a..367c89aca558 100644 > --- a/drivers/gpu/drm/panthor/panthor_mmu.c > +++ b/drivers/gpu/drm/panthor/panthor_mmu.c > @@ -29,6 +29,7 @@ > > #include "panthor_device.h" > #include "panthor_gem.h" > +#include "panthor_gpu.h" > #include "panthor_heap.h" > #include "panthor_mmu.h" > #include "panthor_regs.h" > @@ -568,6 +569,35 @@ static void lock_region(struct panthor_device *ptdev, u32 as_nr, > write_cmd(ptdev, as_nr, AS_COMMAND_LOCK); > } > > +static int mmu_hw_do_flush_on_gpu_ctrl(struct panthor_device *ptdev, int as_nr, > + u32 op) > +{ > + const u32 l2_flush_op = CACHE_CLEAN | CACHE_INV; > + u32 lsc_flush_op = 0; > + int ret; > + > + if (op == AS_COMMAND_FLUSH_MEM) > + lsc_flush_op = CACHE_CLEAN | CACHE_INV; > + > + ret = wait_ready(ptdev, as_nr); > + if (ret) > + return ret; > + > + ret = panthor_gpu_flush_caches(ptdev, l2_flush_op, lsc_flush_op, 0); > + if (ret) > + return ret; > + > + /* > + * Explicitly unlock the region as the AS is not unlocked automatically > + * at the end of the GPU_CONTROL cache flush command, unlike > + * AS_COMMAND_FLUSH_MEM or AS_COMMAND_FLUSH_PT. > + */ > + write_cmd(ptdev, as_nr, AS_COMMAND_UNLOCK); > + > + /* Wait for the unlock command to complete */ > + return wait_ready(ptdev, as_nr); > +} > + > static int mmu_hw_do_operation_locked(struct panthor_device *ptdev, int as_nr, > u64 iova, u64 size, u32 op) > { > @@ -585,6 +615,9 @@ static int mmu_hw_do_operation_locked(struct panthor_device *ptdev, int as_nr, > if (op != AS_COMMAND_UNLOCK) > lock_region(ptdev, as_nr, iova, size); > > + if (op == AS_COMMAND_FLUSH_MEM || op == AS_COMMAND_FLUSH_PT) > + return mmu_hw_do_flush_on_gpu_ctrl(ptdev, as_nr, op); > + > /* Run the MMU operation */ > write_cmd(ptdev, as_nr, op); > > -- > 2.49.0 > -- ==================== | I would like to | | fix the world, | | but they're not | | giving me the | \ source code! / --------------- ¯\_(ツ)_/¯