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AJvYcCUkUibLCWlPRugxtZNswGUcsBCIpPNPhyRalxhabiXNRHQygNpMuoYf+yuG0SaY5ZS/Zay4SEUMymcLTcQ=@vger.kernel.org X-Gm-Message-State: AOJu0YzSR2Sjy9vyTDjOAW95VpfKeAhyPgQCjpvfXvvZZhUcUUipDBSF RlXfeIwOdGW63LCQ4bwDbG5FanxkJIMa1MEvzi1VMvNsrnY0MatAX7395hM/TEIOk3ggigPD1sl 62lXM0w== X-Google-Smtp-Source: AGHT+IHPZf2sNFkisUa9X3++bUjxOogTN/IzAXZHWztCupoH08hlXsip0gsryYc3EdrVWikP1DkEvsEbOgU= X-Received: from pjtu13.prod.google.com ([2002:a17:90a:c88d:b0:312:1e70:e233]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:244a:b0:232:1daf:6f06 with SMTP id d9443c01a7336-23dede94c3fmr61666755ad.47.1752255482578; Fri, 11 Jul 2025 10:38:02 -0700 (PDT) Date: Fri, 11 Jul 2025 10:38:01 -0700 In-Reply-To: <20250711172746.1579423-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250711172746.1579423-1-seanjc@google.com> Message-ID: Subject: Re: [PATCH] KVM: SVM: Emulate PERF_CNTR_GLOBAL_STATUS_SET for PerfMonV2 From: Sean Christopherson To: Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Sandipan Das Content-Type: text/plain; charset="us-ascii" On Fri, Jul 11, 2025, Sean Christopherson wrote: > Emulate PERF_CNTR_GLOBAL_STATUS_SET when PerfMonV2 is enumerated to the > guest, as the MSR is supposed to exist in all AMD v2 PMUs. > > Fixes: 4a2771895ca6 ("KVM: x86/svm/pmu: Add AMD PerfMonV2 support") > Cc: stable@vger.kernel.org > Cc: Sandipan Das > Signed-off-by: Sean Christopherson > --- ... > @@ -711,6 +712,10 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > if (!msr_info->host_initiated) > pmu->global_status &= ~data; > break; > + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET: > + if (!msr_info->host_initiated) > + pmu->global_status |= data & ~pmu->global_status_rsvd; > + break; > default: > kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index); > return kvm_pmu_call(set_msr)(vcpu, msr_info); Tested with a hacky KUT test to verify I got the semantics correct. I think I did? static void test_pmu_msrs(void) { const unsigned long long rsvd = GENMASK_ULL(63, 6); wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, -1ull); report(!rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS), "Wanted '0', got 0x%" PRIx64, rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS)); wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET, -1ull); report(rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS) == ~rsvd, "Wanted '0x%llx', got 0x%" PRIx64, ~rsvd, rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS)); wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, -1ull); report(!rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS), "Wanted '0', got 0x%" PRIx64, rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS)); wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET, 0); report(!rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS), "Wanted '0', got 0x%" PRIx64, rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS)); } One oddity is that the test fails when run on the mediated PMU on Turin, i.e. when the guest can write MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET directly. FAIL: Wanted '0x3f', got 0xc000000000000ff Bits 59:58 failing is expected, because lack of KVM support for DebugCtl[FPCI] and DebugCtl[FLBRI] doesn't remove them from hardware. Disabling interception of MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET creates a virtualization hole on that front, but I don't know that it's worth closing. Letting the guest manually freeze its counters doesn't seem terribly interesting. Bits 7:6 being set is _much_ more interesting, at least to me. They're allegedly reserved per the APM, and CPUID 0x80000022 says there are only 6 counters, so...