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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d5032e9esm177642255e9.3.2025.07.14.10.33.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jul 2025 10:33:44 -0700 (PDT) Date: Mon, 14 Jul 2025 19:33:42 +0200 From: Daniel Lezcano To: Jesse Taube , Anup Patel Cc: linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Thomas Gleixner , Samuel Holland , Conor Dooley , Icenowy Zheng , Jisheng Zhang , linux-kernel@vger.kernel.org Subject: Re: [PATCH v6] clocksource/drivers/timer-clint: Add T-Head C9xx clint Message-ID: References: <20250623231536.1120282-1-Mr.Bossman075@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250623231536.1120282-1-Mr.Bossman075@gmail.com> On Mon, Jun 23, 2025 at 07:15:36PM -0400, Jesse Taube wrote: > From: Jisheng Zhang > > To use the T-HEAD C9xx clint in RISCV-M NOMMU env, we need to take > care two points: > > 1.The mtimecmp in T-Head C9xx clint only supports 32bit read/write, > implement such support. > > 2. As pointed out by commit ca7810aecdba ("lib: utils/timer: mtimer: > add a quirk for lacking mtime register") of opensbi: > > "T-Head developers surely have a different understanding of time CSR and > CLINT's mtime register with SiFive ones, that they did not implement > the mtime register at all -- as shown in openC906 source code, their > time CSR value is just exposed at the top of their processor IP block > and expects an external continous counter, which makes it not > overrideable, and thus mtime register is not implemented, even not for > reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS > extended CSR, these systems still rely on the mtimecmp registers to > generate timer interrupts. This makes it necessary to implement T-Head > C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing > reading mtime register and falls back to default code that reads time > CSR." > > So, we need to fall back to read time CSR instead of mtime register. > Add riscv_csr_time_available static key for this purpose. > > Signed-off-by: Jisheng Zhang > Signed-off-by: Jesse Taube > --- > Treat this as a completely new patch, as it is mostly rewritten. > Original: > https://lore.kernel.org/all/20240410142347.964-3-jszhang@kernel.org/ > V3 -> V4: > - Add riscv,csr-clint > - Allow using of CSRs in S mode > - Change if return else return to if return return > - Change static_branch_likely to static_branch_unlikely > - Fix 32-bit clint_get_cycles64 csr_available check being inverted > - Fix is_c900_clint being uninitialized > V4 -> V5: > - Remove riscv,csr-clint > - Remove riscv_csr_time_available > - Replace all static_branch_unlikely(&riscv_csr_time_available) with > riscv_has_extension_likely(RISCV_ISA_EXT_ZICNTR) > V5 -> V6: > - Add csr_clock_next_event > - Add csr_get_cycles64 to sched_clock_register > - Break get_cycles64 into csr_get_cycles64 and clint_get_cycles64 > - Change default behavior to use CSR time register > > Posible future work: > - Check for SSTC support and use stimercmp > - SSTC depends on smode which cpufeature doesnt check for. > --- I would like to have Anup Patel opinion on these changes -- Daniel -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog