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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d5103c2asm173612365e9.33.2025.07.14.09.18.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jul 2025 09:18:10 -0700 (PDT) Date: Mon, 14 Jul 2025 18:18:08 +0200 From: Daniel Lezcano To: Ben Zong-You Xie Cc: arnd@arndb.de, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, tglx@linutronix.de, prabhakar.mahadev-lad.rj@bp.renesas.com, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, soc@lists.linux.dev, tim609@andestech.com, Conor Dooley Subject: Re: [PATCH v2 5/9] dt-bindings: timer: add Andes machine timer Message-ID: References: <20250711133025.2192404-1-ben717@andestech.com> <20250711133025.2192404-6-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250711133025.2192404-6-ben717@andestech.com> On Fri, Jul 11, 2025 at 09:30:21PM +0800, Ben Zong-You Xie wrote: > Add the DT binding documentation for Andes machine timer. > > The RISC-V architecture defines a machine timer that provides a real-time > counter and generates timer interrupts. Andes machiner timer (PLMT0) is > the implementation of the machine timer, and it contains memory-mapped > registers (mtime and mtimecmp). This device supports up to 32 cores. > > Acked-by: Conor Dooley > Signed-off-by: Ben Zong-You Xie > --- Applied patch 5/9, thanks -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog