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X-CSE-ConnectionGUID: hBtETDJUQTmpoGjaZOog7Q== X-CSE-MsgGUID: hesVyZiXSr2s1irgbzC+pA== X-IronPort-AV: E=McAfee;i="6800,10657,11493"; a="65287731" X-IronPort-AV: E=Sophos;i="6.16,318,1744095600"; d="scan'208";a="65287731" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2025 05:37:11 -0700 X-CSE-ConnectionGUID: b/g5b8dvT4a/3YrLCEJvBQ== X-CSE-MsgGUID: mgLCb2elRau0EXs++y+oVQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,318,1744095600"; d="scan'208";a="162074429" Received: from smile.fi.intel.com ([10.237.72.52]) by orviesa003.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2025 05:37:05 -0700 Received: from andy by smile.fi.intel.com with local (Exim 4.98.2) (envelope-from ) id 1ucNrB-0000000GEkT-1bFt; Thu, 17 Jul 2025 15:37:01 +0300 Date: Thu, 17 Jul 2025 15:37:01 +0300 From: Andy Shevchenko To: Hardevsinh Palaniya Cc: "sakari.ailus@linux.intel.com" , "laurent.pinchart@ideasonboard.com" , "krzk+dt@kernel.org" , Himanshu Bhavani , Mauro Carvalho Chehab , Rob Herring , Conor Dooley , Hans Verkuil , Ricardo Ribalda , Bryan O'Donoghue , Hans de Goede , =?iso-8859-1?Q?Andr=E9?= Apitzsch , Sylvain Petinot , Matthias Fend , Dongcheng Yan , Benjamin Mugnier , Heimir Thor Sverrisson , Jingjing Xiong , Arnd Bergmann , "linux-media@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v4 2/2] media: i2c: add ov2735 image sensor driver Message-ID: References: <20250716134426.8348-1-hardevsinh.palaniya@siliconsignals.io> <20250716134426.8348-3-hardevsinh.palaniya@siliconsignals.io> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Thu, Jul 17, 2025 at 07:26:49AM +0000, Hardevsinh Palaniya wrote: > > On Wed, Jul 16, 2025 at 07:14:17PM +0530, Hardevsinh Palaniya wrote: ... > > > +static int ov2735_page_access(struct ov2735 *ov2735, > > > +                           u32 reg, void *val, int *err, bool is_read) > > > +{ > > > +     u8 page = (reg >> CCI_REG_PRIVATE_SHIFT) & 0xff; > > > +     u32 addr = reg & ~CCI_REG_PRIVATE_MASK; > > > +     int ret = 0; > > > + > > > +     if (err && *err) > > > +             return *err; > > > + > > > +     mutex_lock(&ov2735->page_lock); > > > + > > > +     /* Perform page access before read/write */ > > > +     if (ov2735->current_page != page) { > > > +             ret = cci_write(ov2735->cci, OV2735_REG_PAGE_SELECT, page, &ret); > > > +             if (ret) > > > +                     goto err_mutex_unlock; > > > +             ov2735->current_page = page; > > > +     } > > > + > > > +     if (is_read) > > > +             ret = cci_read(ov2735->cci, addr, (u64 *)val, err); > > > +     else > > > +             ret = cci_write(ov2735->cci, addr, *(u64 *)val, err); > > > + > > > +err_mutex_unlock: > > > > > +     if (ret && err) > > > > Why do you need to check for ret != 0? > > To prevents overwriting *err with 0 on successful operations, which could > obscure previous errors. Can you elaborate a bit how the *err is not 0 at this point (assuming err != NULL)? -- With Best Regards, Andy Shevchenko