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Thu, 17 Jul 2025 13:14:55 -0700 (PDT) Date: Thu, 17 Jul 2025 22:14:51 +0200 From: Stephan Gerhold To: Konrad Dybcio Cc: Yijie Yang , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/4] arm64: dts: qcom: Add HAMOA-IOT-SOM platform Message-ID: References: <20250716-hamoa_initial-v1-0-f6f5d0f9a163@oss.qualcomm.com> <20250716-hamoa_initial-v1-3-f6f5d0f9a163@oss.qualcomm.com> <3a381014-cfe4-4b3c-a3c7-df688c1e87cc@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <3a381014-cfe4-4b3c-a3c7-df688c1e87cc@oss.qualcomm.com> On Thu, Jul 17, 2025 at 10:10:05PM +0200, Konrad Dybcio wrote: > On 7/17/25 6:14 PM, Stephan Gerhold wrote: > > On Wed, Jul 16, 2025 at 05:08:41PM +0800, Yijie Yang wrote: > >> The HAMOA-IOT-SOM is a compact computing module that integrates a System > >> on Chip (SoC) — specifically the x1e80100 — along with essential > >> components optimized for IoT applications. It is designed to be mounted on > >> carrier boards, enabling the development of complete embedded systems. > >> > >> This change enables and overlays the following components: > >> - Regulators on the SOM > >> - Reserved memory regions > >> - PCIe6a and its PHY > >> - PCIe4 and its PHY > >> - USB0 through USB6 and their PHYs > >> - ADSP, CDSP > >> - WLAN, Bluetooth (M.2 interface) > > [...] > > >> +&usb_mp_hsphy0 { > >> + vdd-supply = <&vreg_l2e_0p8>; > >> + vdda12-supply = <&vreg_l3e_1p2>; > >> + > >> + status = "okay"; > >> +}; > >> + > >> +&usb_mp_hsphy1 { > >> + vdd-supply = <&vreg_l2e_0p8>; > >> + vdda12-supply = <&vreg_l3e_1p2>; > >> + > >> + status = "okay"; > >> +}; > >> + > >> +&usb_mp_qmpphy0 { > >> + vdda-phy-supply = <&vreg_l3e_1p2>; > >> + vdda-pll-supply = <&vreg_l3c_0p8>; > >> + > >> + status = "okay"; > >> +}; > >> + > >> +&usb_mp_qmpphy1 { > >> + vdda-phy-supply = <&vreg_l3e_1p2>; > >> + vdda-pll-supply = <&vreg_l3c_0p8>; > >> + > >> + status = "okay"; > >> +}; > >> > > > > Assuming the USB ports are located on the carrier board and not the > > SoM(?): > > > > Are carrier boards required to make use of all these USB > > ports/interfaces? In my experience it's not unusual that embedded > > carrier boards use only the functionality that they need. Maybe this > > should just set the common properties and enabling individual ports for > > PCIe and USB should be up to the carrier boards. > > The PHYs are on the SoC and if the kernel is told they're "disabled", > they may possibly be left dangling from the bootloader > How is this different from any of the laptops we have upstream? If we're worried about firmware keeping unused PHYs on, then we should probably enable all the PHY nodes by default in the SoC .dtsi? Thanks, Stephan