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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?70C3d7X3vPUZGFVpHiC1O6p5g3jH9mGAQdMNtZVS0DOyvfubJUxC6GZSteN5?= =?us-ascii?Q?uTwsQYgdRy1e4moGNtKiBDASsqHpwaFQgfQ0Z4OS26/pOiO3fZuY4UymgGmg?= =?us-ascii?Q?8i4F1hBQcUbd5eRTn1P9n58cNQ6EHXI95osH/LI+NayIKCwuHy0Wyp/LJB0v?= =?us-ascii?Q?z0j8FyGCU+01sJMJntqovVu/6Jk7BmOzaXuT8ldvwirFeZBGS0C1BM/7scxC?= =?us-ascii?Q?kUcXpcDRcC8jHjyCS+RVBj9Aavu3J7nvRnZ+4L7bjwdXNzt/oS9WaPtBhbKx?= =?us-ascii?Q?fvtTjwFXp8UFss2+JBCMlpXwvjgW4g2G/GKDa+jSIWWLKusdNjShK06/g4ej?= =?us-ascii?Q?bWqr9dv/BxqllxvzH4unU4KK9s4hlT9NZAaUhlZI+CMvsi0z8TtfgNECZ1Qr?= =?us-ascii?Q?zlr2aguJ1yzo8Nn6PMGyHxSzHWYPTVTuoZadynIWVLxtSxmcJAgf7eNV7uN0?= =?us-ascii?Q?7335h+BqVQdElhymvjNPGMflGrxosE9dRUjJLKI2gdKKbvRvAjxx3SbbrcNj?= =?us-ascii?Q?Kh/IzUm3EiHuYMQ9unCnDtCMqeAndqwrjWuE9t30fQejBo/2YUbdgL6QohQO?= =?us-ascii?Q?JyglCFBaLDrZBluwSVLOXVA0Dz1zz9DswfwykL02TOKdUd+yAVevtdCQWz/m?= =?us-ascii?Q?y3p7u4jlQDbIl7jOTMXp/HBvEWXq2+akIq83Y+BFBD5GIfNKD9eauso0AmRz?= =?us-ascii?Q?DTr5y4o8DhBcKbyt8ooa1j1KrrfR2QrwYvRFmLOT1oM/eVMPXtixyE2R/uJE?= =?us-ascii?Q?AngrHGqYwb9Ti1rjRkbMHFH4yH7aWraBMG49JMlgWJZdcZu0AiNXAkpmkh9G?= =?us-ascii?Q?ybaPHzzTV6rDUiv1kZCbvRqJAlmMdDH4Y89E92wsPYuR97iNOpr3p9ReqyjI?= =?us-ascii?Q?wsXaq125ts+kFFHK/oAwyPm09wvqxjgyqTqUUXSBrfLnY60huSuYtF5CO33X?= =?us-ascii?Q?DIm7Pohuet/Cvv2w3AuONXzPGShsjQRd0LrtuRjp7sqDmwBlm4Oo6ai9HYw8?= =?us-ascii?Q?pjLW/h+veJ1gOd0o0wkOp8DH+rj2IjsfULMIRw5j3PunqT64SfgXExSS7Dny?= =?us-ascii?Q?sfhMKb5Sawb6fTZe6bTjVWGLyqGSgI7JG99HhNqWfOsecgIjCR4nMgwrlhSo?= =?us-ascii?Q?btCLnK0LEKH21iPITfA4psguoyP9fN44FK6XZw4lTcgMVaj4dFKPdprUdQbR?= =?us-ascii?Q?iPyoJ89lrqt7isoTDmEHvByxFQkdg4bpGlB0BSaS9BlUETsph4cpO71bUidC?= =?us-ascii?Q?K6H+QIyFM2PvT1g/VYuAsch5DrXIW7Z43OYkC3/0TJ1b5ntIKIspwXmBb6W9?= =?us-ascii?Q?/wEMiotbRB2L2iIns40d60+J/17YvLo6zVKr6hvo2ssUSAS6ldXIe5g9i8D3?= =?us-ascii?Q?BSCYavhjgeaHDaM4TBsFER/TD89C2aOdQZWmiVbWodXMSdz2CKBDliAqrJFw?= =?us-ascii?Q?sDdcOBZFkGGy5wSB4iZ0ad2r/l505MZN5DTkUh5SG1CY9KXkcxy9XEveHKep?= =?us-ascii?Q?jMHs5A8HgWOdc6vV7/dLtfR+QL79ryiN7pVjVEcmxawOGNfcXgPxeNs9db80?= =?us-ascii?Q?r0qdd3PLElaUlPf/ZrY=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 793cdae9-1cc4-48f1-8ad9-08ddcb81886d X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jul 2025 13:45:35.8541 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: HUXmz3hGzuM9NEG3z4m03su5pkcWHkoc2MSvBxeMQnDBOpaCRT5k6aesUlD1ETUIJzBs7MS+RSPzpcA15ziZqQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU4PR04MB11409 On Fri, Jul 25, 2025 at 03:03:10PM +0800, Stanley Chu wrote: > From: Stanley Chu > > Prefilling in private write transfers is only necessary when the FIFO > is empty. Otherwise, if the transfer is NACKed due to IBIWON and retries > continue, data may be prefilled again but could be lost because the FIFO > is not empty. why "maybe prefilled", please use certain words. > > Fixes: 4008a74e0f9b ("i3c: master: svc: Fix npcm845 FIFO empty issue") > Signed-off-by: Stanley Chu > --- > drivers/i3c/master/svc-i3c-master.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c > index 7e1a7cb94b43..34b6e125b18a 100644 > --- a/drivers/i3c/master/svc-i3c-master.c > +++ b/drivers/i3c/master/svc-i3c-master.c > @@ -104,6 +104,7 @@ > #define SVC_I3C_MDATACTRL_TXTRIG_FIFO_NOT_FULL GENMASK(5, 4) > #define SVC_I3C_MDATACTRL_RXTRIG_FIFO_NOT_EMPTY 0 > #define SVC_I3C_MDATACTRL_RXCOUNT(x) FIELD_GET(GENMASK(28, 24), (x)) > +#define SVC_I3C_MDATACTRL_TXCOUNT(x) FIELD_GET(GENMASK(20, 16), (x)) > #define SVC_I3C_MDATACTRL_TXFULL BIT(30) > #define SVC_I3C_MDATACTRL_RXEMPTY BIT(31) > > @@ -280,6 +281,13 @@ static inline bool is_events_enabled(struct svc_i3c_master *master, u32 mask) > return !!(master->enabled_events & mask); > } > > +static inline bool svc_i3c_master_tx_empty(struct svc_i3c_master *master) > +{ > + u32 reg = readl(master->regs + SVC_I3C_MDATACTRL); > + > + return (SVC_I3C_MDATACTRL_TXCOUNT(reg) == 0); > +} > + > static bool svc_i3c_master_error(struct svc_i3c_master *master) > { > u32 mstatus, merrwarn; > @@ -1303,7 +1311,8 @@ static int svc_i3c_master_xfer(struct svc_i3c_master *master, > * The only way to work around this hardware issue is to let the > * FIFO start filling as soon as possible after EmitStartAddr. > */ > - if (svc_has_quirk(master, SVC_I3C_QUIRK_FIFO_EMPTY) && !rnw && xfer_len) { > + if (svc_has_quirk(master, SVC_I3C_QUIRK_FIFO_EMPTY) && !rnw && xfer_len && > + svc_i3c_master_tx_empty(master)) { > u32 end = xfer_len > SVC_I3C_FIFO_SIZE ? 0 : SVC_I3C_MWDATAB_END; > u32 len = min_t(u32, xfer_len, SVC_I3C_FIFO_SIZE); if prefill to FIFO SIZE each time, such as replace SVC_I3C_FIFO_SIZE with SVC_I3C_FIFO_SIZE - SVC_I3C_MDATACTRL_TXCOUNT(readl(master->regs + SVC_I3C_MDATACTRL)). Frank > > -- > 2.34.1 >