From: Varadarajan Narayanan <quic_varada@quicinc.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: <andersson@kernel.org>, <mturquette@baylibre.com>,
<sboyd@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,
<conor+dt@kernel.org>, <konradybcio@kernel.org>,
<rafael@kernel.org>, <viresh.kumar@linaro.org>,
<ilia.lin@kernel.org>, <djakov@kernel.org>,
<linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-pm@vger.kernel.org>,
"Sricharan Ramabadhran" <quic_srichara@quicinc.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Md Sadre Alam <quic_mdalam@quicinc.com>
Subject: Re: [PATCH v6 1/4] dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller
Date: Thu, 7 Aug 2025 10:08:34 +0530 [thread overview]
Message-ID: <aJQtyouomCxI8Rfa@hu-varada-blr.qualcomm.com> (raw)
In-Reply-To: <70bd9beb-2f7f-4132-88a4-8d81d70ac50b@kernel.org>
On Wed, Aug 06, 2025 at 01:47:34PM +0200, Krzysztof Kozlowski wrote:
> On 06/08/2025 13:28, Varadarajan Narayanan wrote:
> > From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> >
> > The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
> > The RCG and PLL have a separate register space from the GCC.
> > Also the L3 cache has a separate pll and needs to be scaled along
> > with the CPU.
> >
> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> This is oddly placed. Did you use b4 that it appeared here?
b4 places like this
Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
[ Added interconnect related changes ]
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Since I haven't seen Reviewed-by coming after Signed-off-by, Was not
sure if my Signed-off-by should come before or after the Reviewed-by.
So, manually placed it there. If this is not ok, will use how b4's
placement itself and post the next version. Kindly, let me know.
Thanks
Varada
> > Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> > Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> > [ Added interconnect related changes ]
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
> > v6: Add 'Reviewed-by: Krzysztof Kozlowski'
> > Drop 'clock-names'
>
> Best regards,
> Krzysztof
next prev parent reply other threads:[~2025-08-07 4:38 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-06 11:28 [PATCH v6 0/4] Enable cpufreq for IPQ5424 Varadarajan Narayanan
2025-08-06 11:28 ` [PATCH v6 1/4] dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller Varadarajan Narayanan
2025-08-06 11:47 ` Krzysztof Kozlowski
2025-08-07 4:38 ` Varadarajan Narayanan [this message]
2025-08-06 11:28 ` [PATCH v6 2/4] clk: qcom: apss-ipq5424: " Varadarajan Narayanan
2025-08-06 12:35 ` Konrad Dybcio
2025-08-06 11:28 ` [PATCH v6 3/4] cpufreq: qcom-nvmem: Enable cpufreq for ipq5424 Varadarajan Narayanan
2025-08-11 7:01 ` Viresh Kumar
2025-08-06 11:28 ` [PATCH v6 4/4] arm64: dts: qcom: ipq5424: Enable cpufreq Varadarajan Narayanan
2025-08-07 12:57 ` Konrad Dybcio
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