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From: Oleksij Rempel <o.rempel@pengutronix.de>
To: Andrew Lunn <andrew@lunn.ch>
Cc: "Russell King (Oracle)" <linux@armlinux.org.uk>,
	Xu Yang <xu.yang_2@nxp.com>,
	hkallweit1@gmail.com, pabeni@redhat.com, netdev@vger.kernel.org,
	imx@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [RESEND] net: phy: fix NULL pointer dereference in phy_polling_mode()
Date: Thu, 7 Aug 2025 16:02:31 +0200	[thread overview]
Message-ID: <aJSx9xTrFfFm0dcx@pengutronix.de> (raw)
In-Reply-To: <d137518b-604b-4be3-9eb1-96d49123a251@lunn.ch>

On Thu, Aug 07, 2025 at 02:58:05PM +0200, Andrew Lunn wrote:
> > Hm, I guess, with this change there will be a subtile regression.
> > In case of an external PHYs the ax88772_init_phy() is using PHYlib to
> > suspend the internal PHY.
> > 
> > May be:
> >   priv->mdio->phy_mask = ~(BIT(priv->phy_addr) | BIT(AX_EMBD_PHY_ADDR));
> 
> I looked at that:

Here we read the primary PHY address from the EEPROM. This offset may
contain either the internal or external PHY address. See commit
d0ffff8fddd5 ("USB: asix: Detect internal PHY and enable/use
accordingly")

I need to admit, asix_read_phy_addr(..., bool internal) was originally
designed to distinguish between internal and external PHYs by setting
internal = false.  But in practice, most vendors seem to follow the
existing driver behavior as reference, and only modify the primary PHY
address in the EEPROM.

> 	ret = asix_read_phy_addr(dev, true);
> 	if (ret < 0)
> 		return ret;
> 

At this point, we store the address of the internal or external PHY:

> 	priv->phy_addr = ret;

If the PHY address matches the address of the internal PHY, then
embd_phy is set to true:

> 	priv->embd_phy = ((priv->phy_addr & 0x1f) == AX_EMBD_PHY_ADDR);
> 
> So priv->phy_addr has to be the address of the internal PHY, so this
> should just work without anything special for the embedded PHY.

For most AX88772-based devices, priv->phy_addr is indeed the internal
PHY. However, on devices with an external PHY - like the "Linux
Automation GmbH USB 10Base-T1L" - both internal and external PHYs are
accessible over the MDIO bus.

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  reply	other threads:[~2025-08-07 14:02 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-06  8:29 Xu Yang
2025-08-06  8:45 ` Russell King (Oracle)
2025-08-06  8:56   ` Xu Yang
2025-08-06 13:01     ` Russell King (Oracle)
2025-08-06 14:14       ` Xu Yang
2025-08-06 15:01         ` Andrew Lunn
2025-08-06 16:47           ` Russell King (Oracle)
2025-08-07  9:23             ` Xu Yang
2025-08-07 11:21               ` Xu Yang
2025-08-07 11:47                 ` Russell King (Oracle)
2025-08-07 12:45                   ` Oleksij Rempel
2025-08-07 12:58                     ` Andrew Lunn
2025-08-07 14:02                       ` Oleksij Rempel [this message]
2025-08-08 10:26                     ` Xu Yang
2025-08-08 10:17                   ` Xu Yang
2025-08-07 12:55                 ` Andrew Lunn
2025-08-07  9:10           ` Xu Yang

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