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[83.60.94.205]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459db3048bdsm390721525e9.29.2025.08.12.02.24.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Aug 2025 02:24:25 -0700 (PDT) From: Jorge Ramirez X-Google-Original-From: Jorge Ramirez Date: Tue, 12 Aug 2025 11:24:24 +0200 To: Neil Armstrong Cc: Dikshita Agarwal , Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] media: iris: vpu3x: Add MNoC low power handshake during hardware power-off Message-ID: References: <20250812-sm8650-power-sequence-fix-v1-1-a51e7f99c56c@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA5MDAzNSBTYWx0ZWRfX7CLL/SMTDtkU M6ZYyNQBip2DNfYLe92ivF1mUdoQUt8WQCVa8Y4wof4uapNaG2pDd/oNwBu3zeI9r1z8nn7AyZp G/lmV2YRg9YCWeSsEDSScgJ/upE+KUopSLpy/wn8kuY3UErIKwx/MJzZT6LsGaxBl1FWaVea+ee m3+S4l8q0hJLS/Yfx0UBCmzHQ9LTPffcHEGAgGEPwdKHEwBKiqprfZRO3ikSpRuL3yURJyaG9eX eRJeUr+vIwoghkdrDyWnKMzxujfer+kR+Jw19ghzcDuT4MGO2a3bKxGoMW1wBBohExjA94PyPMs 5U7fJcEWGCNcvbHQ0MyUYfVc20LcWG9UJ3euGxumB1wxCEH50+/dxr5A8q97blfrSC7Oct5zBSJ JiK4aSb7 X-Authority-Analysis: v=2.4 cv=FvMF/3rq c=1 sm=1 tr=0 ts=689b084b cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=Rr2dNH5/fcnoRoBmcVUeRg==:17 a=kj9zAlcOel0A:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=Ovw8jLjI9PxWGIGDV-AA:9 a=CjuIK1q_8ugA:10 a=uxP6HrT_eTzRwkO_Te1X:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: eBB-VivFDZplzDxeKV8if3CmTqbBcU6v X-Proofpoint-ORIG-GUID: eBB-VivFDZplzDxeKV8if3CmTqbBcU6v X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_04,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 bulkscore=0 suspectscore=0 phishscore=0 clxscore=1015 impostorscore=0 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508090035 On 12/08/25 10:06:40, Neil Armstrong wrote: > On 12/08/2025 09:48, Dikshita Agarwal wrote: > > Add the missing write to AON_WRAPPER_MVP_NOC_LPI_CONTROL before > > reading the LPI status register. Introduce a handshake loop to ensure > > MNoC enters low power mode reliably during VPU3 hardware power-off with > > timeout handling. > > > > Signed-off-by: Dikshita Agarwal > > --- > > drivers/media/platform/qcom/iris/iris_vpu3x.c | 23 +++++++++++++++++++++-- > > 1 file changed, 21 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c > > index 9b7c9a1495ee2f51c60b1142b2ed4680ff798f0a..c2e6af575cbe4b3e3f2a019b24eecf3a5d469566 100644 > > --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c > > +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c > > @@ -110,6 +110,7 @@ static void iris_vpu3_power_off_hardware(struct iris_core *core) > > static void iris_vpu33_power_off_hardware(struct iris_core *core) > > { > > u32 reg_val = 0, value, i; > > + u32 count = 0; > > int ret; > > if (iris_vpu3x_hw_power_collapsed(core)) > > @@ -128,13 +129,31 @@ static void iris_vpu33_power_off_hardware(struct iris_core *core) > > goto disable_power; > > } > > + /* set MNoC to low power */ > > + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); > > + > > + value = readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS); > > + for readibility purposes, could this code be restructed a bit differently? maybe all the write/read operations in a single do while loop with the exit conditions assigned to variables with an identifiable meaning? maybe also check/report errors outside the loop itself? > > + while (!(value & BIT(0)) && (value & BIT(2) || value & BIT(1))) { > > + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); > > + > > + usleep_range(10, 20); > > + > > + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); > > + > > + value = readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS); > > + if (++count >= 1000) { > > + dev_err(core->dev, "LPI handshake timeout\n"); > > + break; > > + } > > + } > > + > > ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, > > reg_val, reg_val & BIT(0), 200, 2000); > > if (ret) > > goto disable_power; > > - /* set MNoC to low power, set PD_NOC_QREQ (bit 0) */ > > - writel(BIT(0), core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); > > + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); > > writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, > > core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); > > > > --- > > base-commit: d968e50b5c26642754492dea23cbd3592bde62d8 > > change-id: 20250812-sm8650-power-sequence-fix-ba9a92098233 > > > > Best regards, > > Tested-by: Neil Armstrong # on SM8650-HDK > > Thanks, > Neil >