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Wed, 27 Aug 2025 08:47:50 -0700 Date: Wed, 27 Aug 2025 08:47:48 -0700 From: Nicolin Chen To: Suravee Suthikulpanit CC: , , , , , , , , , , , , , , , , Subject: Re: [PATCH v2] iommu/amd: Add support for hw_info for iommu capability query Message-ID: References: <20250827142250.5594-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250827142250.5594-1-suravee.suthikulpanit@amd.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F1:EE_|DS2PR12MB9774:EE_ X-MS-Office365-Filtering-Correlation-Id: 91a0bc60-93b6-41ad-3ec3-08dde581218f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|36860700013|82310400026|7053199007; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2025 15:48:13.0724 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 91a0bc60-93b6-41ad-3ec3-08dde581218f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9774 On Wed, Aug 27, 2025 at 02:22:50PM +0000, Suravee Suthikulpanit wrote: > AMD IOMMU Extended Feature (EFR) and Extended Feature 2 (EFR2) registers > specify features supported by each IOMMU hardware instance. > The IOMMU driver checks each feature-specific bits before enabling > each feature at run time. > > For IOMMUFD, the hypervisor passes the raw value of amd_iommu_efr and > amd_iommu_efr2 to VMM via iommufd IOMMU_DEVICE_GET_HW_INFO ioctl. > > Signed-off-by: Suravee Suthikulpanit Reviewed-by: Nicolin Chen With some nits: > diff --git a/drivers/iommu/amd/iommufd.h b/drivers/iommu/amd/iommufd.h > new file mode 100644 > index 000000000000..7c30dcc66a59 > --- /dev/null > +++ b/drivers/iommu/amd/iommufd.h > @@ -0,0 +1,11 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (C) 2025 Advanced Micro Devices, Inc. > + */ > + > +#ifndef AMD_IOMMUFD_H > +#define AMD_IOMMUFD_H > + > +extern void *amd_iommufd_hw_info(struct device *dev, u32 *length, u32 *type); No need of "extern"? > +/** > + * struct iommu_hw_info_amd - AMD IOMMU device info > + * > + * @efr : Value of AMD IOMMU Extended Feature Register (EFR) reported by hardware > + * @efr2: Value of AMD IOMMU Extended Feature 2 Register (EFR2) reported by hardware > + * > + * Please See description of these registers in the following sections of > + * the AMD I/O Virtualization Technology (IOMMU) Specification. > + * (https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_IOMMU.pdf) The link gives me: 404: Page Not Found Sorry, we couldn’t find that page. :-/ > /** > * enum iommu_hw_info_type - IOMMU Hardware Info Types > * @IOMMU_HW_INFO_TYPE_NONE: Output by the drivers that do not report hardware > @@ -629,6 +647,7 @@ enum iommu_hw_info_type { > IOMMU_HW_INFO_TYPE_INTEL_VTD = 1, > IOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2, > IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3, > + IOMMU_HW_INFO_TYPE_AMD = 4, Missing an update in the kdoc above. Nicolin