From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E99851C84C0; Sat, 16 Aug 2025 19:55:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755374126; cv=none; b=TLhM8eBqDd2qRyHf7UN/qnDqHyix8B+0ytABLiMkEjhNUW6h7kSb8X6iN7/eiqZAgDHRlKDUCYCBqSfEnHxlgD/iRlqCgTQmg2+7Ix035H1jBi4M3S3al1le9glPh7PptJLiWg5KQIIb39NWyaeI2VmI2U092w48HdJBPHn7vl8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755374126; c=relaxed/simple; bh=Tm/e6LdOIS4eu+0O16MIPxMpl1cBxbzWq6QHW8ji5kE=; h=Date:From:To:Cc:Subject:Message-ID:MIME-Version:Content-Type: Content-Disposition; b=OtJvZEq36Me8FKqDt2XRBTH2hy+vO5nWs5NJGT+ZQx0XTAxP9cSMUGcFu0AroZIY6GOyBdTOsY8cCi6c1nvtbuwWF3y/IYSe24w7WuGV5PDGEsGBw0DvRxkLYUDIDKOX0djkx60wkP/r2Gp+O0NJz/cqIPsgOnP0aMt+J26znCw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.98.2) (envelope-from ) id 1unMzm-0000000074u-1RPh; Sat, 16 Aug 2025 19:55:18 +0000 Date: Sat, 16 Aug 2025 20:55:14 +0100 From: Daniel Golle To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Hauke Mehrtens , Simon Horman , Russell King , Florian Fainelli , Arkadi Sharshevsky , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Andreas Schirm , Lukas Stockmann , Alexander Sverdlin , Peter Christen , Avinash Jayaraman , Bing tao Xu , Liang Xu , Juraj Povazanec , "Fanni (Fang-Yi) Chan" , "Benny (Ying-Tsan) Weng" , "Livia M. Rosu" , John Crispin Subject: [PATCH RFC net-next 15/23] net: dsa: lantiq_gswip: allow adjusting MII delays Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Currently the MII clk vs. data delay is configured based on the PHY interface mode. In addition to that add support for setting up MII delays using the standard Device Tree properties 'tx-internal-delay-ps' and 'rx-internal-delay-ps' and only fall back to using the PHY interface mode in case both properties are unused. Signed-off-by: Daniel Golle --- drivers/net/dsa/lantiq_gswip.c | 30 ++++++++++++++++++++++++++++++ drivers/net/dsa/lantiq_gswip.h | 4 ++++ 2 files changed, 34 insertions(+) diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c index e67950c69978..6eae4fcb99e6 100644 --- a/drivers/net/dsa/lantiq_gswip.c +++ b/drivers/net/dsa/lantiq_gswip.c @@ -586,6 +586,33 @@ static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port, return 0; } +static bool gswip_mii_delay_setup(struct gswip_priv *priv, struct dsa_port *dp) +{ + u32 tx_delay = GSWIP_MII_PCDU_TXDLY_DEFAULT; + u32 rx_delay = GSWIP_MII_PCDU_RXDLY_DEFAULT; + struct device_node *port_dn = dp->dn; + bool used; + int ret; + + ret = of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); + if (ret && ret != -EINVAL) + return ret; + used = !ret; + + ret = of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); + if (ret && ret != -EINVAL) + return ret; + used |= !ret; + + if (used) + gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK | + GSWIP_MII_PCDU_RXDLY_MASK, + GSWIP_MII_PCDU_TXDLY(tx_delay) | + GSWIP_MII_PCDU_RXDLY(rx_delay), dp->index); + + return used; +} + static int gswip_setup(struct dsa_switch *ds) { unsigned int cpu_ports = dsa_cpu_ports(ds); @@ -1521,6 +1548,9 @@ static void gswip_phylink_mac_config(struct phylink_config *config, GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS, miicfg, port); + if (gswip_mii_delay_setup(priv, dp)) + return; + switch (state->interface) { case PHY_INTERFACE_MODE_RGMII_ID: gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK | diff --git a/drivers/net/dsa/lantiq_gswip.h b/drivers/net/dsa/lantiq_gswip.h index 5bc47c329620..1b97842b77e7 100644 --- a/drivers/net/dsa/lantiq_gswip.h +++ b/drivers/net/dsa/lantiq_gswip.h @@ -82,6 +82,10 @@ #define GSWIP_MII_PCDU5 0x05 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0) #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7) +#define GSWIP_MII_PCDU_TXDLY(x) u16_encode_bits(((x) / 500), GSWIP_MII_PCDU_TXDLY_MASK) +#define GSWIP_MII_PCDU_RXDLY(x) u16_encode_bits(((x) / 500), GSWIP_MII_PCDU_RXDLY_MASK) +#define GSWIP_MII_PCDU_RXDLY_DEFAULT 2000 /* picoseconds */ +#define GSWIP_MII_PCDU_TXDLY_DEFAULT 2000 /* picoseconds */ /* GSWIP Core Registers */ #define GSWIP_SWRES 0x000 -- 2.50.1