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Peter Anvin" , jgross@suse.com, "Kirill A. Shutemov" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Ingo Molnar , pbonzini@redhat.com, Peter Gonda , Thomas Gleixner , Tom Lendacky , Vitaly Kuznetsov , x86@kernel.org, Rick Edgecombe , jiewen.yao@intel.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Thu, Aug 21, 2025, Binbin Wu wrote: > On 8/21/2025 11:30 AM, Binbin Wu wrote: > > Variable MTRR has requirement for range size and alignment: > > For ranges greater than 4 KBytes, each range must be of length 2^n and = its base > > address must be aligned on a 2^n boundary, where n is a value equal to = or > > greater than 12. The base-address alignment value cannot be less than i= ts length. >=20 > Wait, Linux kernel converts MTRR register values to MTRR state (base and = size) and > cache it for later lookups (refer to map_add_var()). I.e., in Linux kerne= l, > only the cached state will be used. >=20 > These MTRR register values are never programmed when using > guest_force_mtrr_state() , so even the values doesn't meet the requiremen= t > from hardware perspective, Linux kernel can still get the right base and > size. Yeah. I forget what happens if the ranges don't meet the power-of-2 requir= ements, but the mask+match logic should work jus tfine. > No bothering to force the base and size alignment. > But a comment would be helpful. > Also, BIT(11) could be replaced by MTRR_PHYSMASK_V. Ha! I spent a good 5 minutes looking for a #define couldn't find one. Wha= t a bizarre name... > How about: > diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c > index 90097df4eafd..a9582ffc3088 100644 > --- a/arch/x86/kernel/kvm.c > +++ b/arch/x86/kernel/kvm.c > @@ -934,9 +934,15 @@ static void kvm_sev_hc_page_enc_status(unsigned long= pfn, int npages, bool enc) > =C2=A0static void __init kvm_init_platform(void) > =C2=A0{ > =C2=A0 =C2=A0 =C2=A0 =C2=A0 u64 tolud =3D e820__end_of_low_ram_pfn() << P= AGE_SHIFT; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0/* > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 * The range's base address and size may not = meet the alignment > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 * requirement for variable MTRR. However, Li= nux guest never > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 * programs MTRRs when forcing guest MTRR sta= te, no bothering to > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 * enforce the base and range size alignment. > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 */ > =C2=A0 =C2=A0 =C2=A0 =C2=A0 struct mtrr_var_range pci_hole =3D { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 .base_lo =3D tolu= d | X86_MEMTYPE_UC, > -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.mask_lo =3D (u32= )(~(SZ_4G - tolud - 1)) | BIT(11), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.mask_lo =3D (u32= )(~(SZ_4G - tolud - 1)) | MTRR_PHYSMASK_V, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 .mask_hi =3D (BIT= _ULL(boot_cpu_data.x86_phys_bits) - 1) >> 32, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 }; >=20 >=20 > I tested it in my setup, it can fix the issue of TPM driver failure with = the > modified ACPI table for TPM in QEMU. >=20 >=20 > Hi Vishal, > Could you test it with google's VMM? Vishal is OOO for a few days. I pinged our internal bug tracker, I'll find someone to test. Thanks much!