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Thu, 4 Sep 2025 09:51:47 +0000 Date: Thu, 4 Sep 2025 17:50:49 +0800 From: Yan Zhao To: Binbin Wu CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [RFC PATCH v2 18/23] x86/virt/tdx: Do not perform cache flushes unless CLFLUSH_BEFORE_ALLOC is set Message-ID: Reply-To: Yan Zhao References: <20250807093950.4395-1-yan.y.zhao@intel.com> <20250807094516.4705-1-yan.y.zhao@intel.com> <0d3229ff-2359-4ade-a715-c8af56c2916c@linux.intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <0d3229ff-2359-4ade-a715-c8af56c2916c@linux.intel.com> X-ClientProxiedBy: SI2PR02CA0040.apcprd02.prod.outlook.com (2603:1096:4:196::6) To DS7PR11MB5966.namprd11.prod.outlook.com (2603:10b6:8:71::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS7PR11MB5966:EE_|SN7PR11MB7419:EE_ X-MS-Office365-Filtering-Correlation-Id: d08e4240-4fc9-45ac-86b9-08ddeb98a9e7 X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|1800799024|7416014; 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Shutemov" > > > > The TDX module enumerates with a TDX_FEATURES0 bit if an explicit cache > > flush is necessary when switching KeyID for a page, like before > > handing the page over to a TD. > > > > Currently, none of the TDX-capable platforms have this bit enabled. > > > > Moreover, cache flushing with TDH.PHYMEM.PAGE.WBINVD fails if > > Dynamic PAMT is active and the target page is not 4k. The SEAMCALL only > > supports 4k pages and will fail if there is no PAMT_4K for the HPA. > > > > Avoid performing these cache flushes unless the CLFLUSH_BEFORE_ALLOC bit > > of TDX_FEATURES0 is set. > > > > Signed-off-by: Kirill A. Shutemov > > Signed-off-by: Yan Zhao > > --- > > RFC v2: > > - Pulled from > > git://git.kernel.org/pub/scm/linux/kernel/git/kas/linux.git tdx/dpamt-huge. > > - Rebased on top of TDX huge page RFC v2 (Yan) > > --- > > arch/x86/include/asm/tdx.h | 1 + > > arch/x86/virt/vmx/tdx/tdx.c | 19 +++++++++++++------ > > 2 files changed, 14 insertions(+), 6 deletions(-) > > > > diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h > > index f1bd74348b34..c058a82d4a97 100644 > > --- a/arch/x86/include/asm/tdx.h > > +++ b/arch/x86/include/asm/tdx.h > > @@ -15,6 +15,7 @@ > > /* Bit definitions of TDX_FEATURES0 metadata field */ > > #define TDX_FEATURES0_NO_RBP_MOD BIT_ULL(18) > > +#define TDX_FEATURES0_CLFLUSH_BEFORE_ALLOC BIT_ULL(23) > > #define TDX_FEATURES0_DYNAMIC_PAMT BIT_ULL(36) > > #ifndef __ASSEMBLER__ > > diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c > > index 9ed585bde062..b7a0ee0f4a50 100644 > > --- a/arch/x86/virt/vmx/tdx/tdx.c > > +++ b/arch/x86/virt/vmx/tdx/tdx.c > > @@ -1648,14 +1648,13 @@ static inline u64 tdx_tdvpr_pa(struct tdx_vp *td) > > return page_to_phys(td->tdvpr_page); > > } > > -/* > > - * The TDX module exposes a CLFLUSH_BEFORE_ALLOC bit to specify whether > > - * a CLFLUSH of pages is required before handing them to the TDX module. > > - * Be conservative and make the code simpler by doing the CLFLUSH > > - * unconditionally. > > - */ > > static void tdx_clflush_page(struct page *page) > > { > > + u64 tdx_features0 = tdx_sysinfo.features.tdx_features0; > > + > > + if (tdx_features0 & TDX_FEATURES0_CLFLUSH_BEFORE_ALLOC) > > According to the cover letter, if TDX_FEATURES0_CLFLUSH_BEFORE_ALLOC is enabled, > an explicit cache flush is necessary. > Shouldn't this and below be: > if (!(tdx_features0 & TDX_FEATURES0_CLFLUSH_BEFORE_ALLOC)) Right, Sagi also reported it. https://lore.kernel.org/kvm/CAAhR5DEZZfX0=9QwBrXhC+1fp1Z0w4Xbb3mXcn0OuW+45tsLwA@mail.gmail.com/ > > + return; > > + > > clflush_cache_range(page_to_virt(page), PAGE_SIZE); > > } > > @@ -2030,8 +2029,12 @@ EXPORT_SYMBOL_GPL(tdh_phymem_cache_wb); > > u64 tdh_phymem_page_wbinvd_tdr(struct tdx_td *td) > > { > > + u64 tdx_features0 = tdx_sysinfo.features.tdx_features0; > > struct tdx_module_args args = {}; > > + if (tdx_features0 & TDX_FEATURES0_CLFLUSH_BEFORE_ALLOC) > > + return 0; > > + > > args.rcx = mk_keyed_paddr(tdx_global_keyid, td->tdr_page); > > return seamcall(TDH_PHYMEM_PAGE_WBINVD, &args); > > @@ -2041,10 +2044,14 @@ EXPORT_SYMBOL_GPL(tdh_phymem_page_wbinvd_tdr); > > u64 tdh_phymem_page_wbinvd_hkid(u64 hkid, struct folio *folio, > > unsigned long start_idx, unsigned long npages) > > { > > + u64 tdx_features0 = tdx_sysinfo.features.tdx_features0; > > struct page *start = folio_page(folio, start_idx); > > struct tdx_module_args args = {}; > > u64 err; > > + if (tdx_features0 & TDX_FEATURES0_CLFLUSH_BEFORE_ALLOC) > > + return 0; > > + > > if (start_idx + npages > folio_nr_pages(folio)) > > return TDX_OPERAND_INVALID; >