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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <3b691f3a-633c-4a7f-bc38-a9c464d83fe1@oss.qualcomm.com> X-Authority-Analysis: v=2.4 cv=OemYDgTY c=1 sm=1 tr=0 ts=68b9b04e cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=7jlciowUQMUDIi_Z8n8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: 4oGLf9XvW6rwbCt4wjdyn5zsGktY8b5b X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAyNCBTYWx0ZWRfX5WTBf3qWGYUz l01NFyJEd0gCN/LlBx1b+9QPQz/J28Tldod3HZwOVlYxnEyYo9yW6ZwC8KR8DyxyoUofOKlbxhV BMe3GcA5o7U/K5q2aNot/Xn4ih6UwCsO8rA+DK1Hr+up5jf9ZBHh16myIgpOtr9uPKdICsx9Gz5 6ObZ0jAwx8QR7Ub4wIVKIfwwLkuk3vwrF2hD95FT0M+iMeXhqio3GbPkaHBU3v8g6WAT1O4maug 7/05VWDUrY2lNb+VZk+I0m8KxPtGq0v2apwGP3ub+D61wSW1bZ+ttxZpf44Z3pzRn4sORl2d/1U 70YZad2XUo1nfP3JH+nrQviEihWSreyhm9zQJRSi5EGdHHmbanuEPUai0ybh4rdnAzDP5S79vhC 1bYwj/pQ X-Proofpoint-ORIG-GUID: 4oGLf9XvW6rwbCt4wjdyn5zsGktY8b5b X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-04_05,2025-09-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 spamscore=0 bulkscore=0 priorityscore=1501 adultscore=0 clxscore=1015 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300024 On Thu, Sep 04, 2025 at 04:34:05PM +0200, Konrad Dybcio wrote: > On 9/4/25 3:35 PM, Dmitry Baryshkov wrote: > > On Wed, Sep 03, 2025 at 09:58:33PM +0530, Wasim Nazir wrote: > >> On Wed, Sep 03, 2025 at 06:12:59PM +0200, Konrad Dybcio wrote: > >>> On 8/27/25 3:20 AM, Dmitry Baryshkov wrote: > >>>> On Tue, Aug 26, 2025 at 11:51:01PM +0530, Wasim Nazir wrote: > >>>>> From: Monish Chunara > >>>>> > >>>>> Introduce the SDHC v5 controller node for the Lemans platform. > >>>>> This controller supports either eMMC or SD-card, but only one > >>>>> can be active at a time. SD-card is the preferred configuration > >>>>> on Lemans targets, so describe this controller. > >>>>> > >>>>> Define the SDC interface pins including clk, cmd, and data lines > >>>>> to enable proper communication with the SDHC controller. > >>>>> > >>>>> Signed-off-by: Monish Chunara > >>>>> Co-developed-by: Wasim Nazir > >>>>> Signed-off-by: Wasim Nazir > >>>>> --- > >>>>> arch/arm64/boot/dts/qcom/lemans.dtsi | 70 ++++++++++++++++++++++++++++++++++++ > >>>>> 1 file changed, 70 insertions(+) > >>>>> > >>>>> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi > >>>>> index 99a566b42ef2..a5a3cdba47f3 100644 > >>>>> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi > >>>>> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi > >>>>> @@ -3834,6 +3834,36 @@ apss_tpdm2_out: endpoint { > >>>>> }; > >>>>> }; > >>>>> > >>>>> + sdhc: mmc@87c4000 { > >>>>> + compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5"; > >>>>> + reg = <0x0 0x087c4000 0x0 0x1000>; > >>>>> + > >>>>> + interrupts = , > >>>>> + ; > >>>>> + interrupt-names = "hc_irq", "pwr_irq"; > >>>>> + > >>>>> + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > >>>>> + <&gcc GCC_SDCC1_APPS_CLK>; > >>>>> + clock-names = "iface", "core"; > >>>>> + > >>>>> + interconnects = <&aggre1_noc MASTER_SDC 0 &mc_virt SLAVE_EBI1 0>, > >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDC1 0>; > >>>>> + interconnect-names = "sdhc-ddr", "cpu-sdhc"; > >>>>> + > >>>>> + iommus = <&apps_smmu 0x0 0x0>; > >>>>> + dma-coherent; > >>>>> + > >>>>> + resets = <&gcc GCC_SDCC1_BCR>; > >>>>> + > >>>>> + no-sdio; > >>>>> + no-mmc; > >>>>> + bus-width = <4>; > >>>> > >>>> This is the board configuration, it should be defined in the EVK DTS. > >>> > >>> Unless the controller is actually incapable of doing non-SDCards > >>> > >>> But from the limited information I can find, this one should be able > >>> to do both > >>> > >> > >> It’s doable, but the bus width differs when this controller is used for > >> eMMC, which is supported on the Mezz board. So, it’s cleaner to define > >> only what’s needed for each specific usecase on the board. > > > > `git grep no-sdio arch/arm64/boot/dts/qcom/` shows that we have those > > properties inside the board DT. I don't see a reason to deviate. > > Just to make sure we're clear > > I want the author to keep bus-width in SoC dt and move the other > properties to the board dt > I'll move the no-sdio and no-mmc properties to the board-specific device tree file, and keep the bus-width configuration in the SoC-level file. -- Regards, Wasim