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Sat, 06 Sep 2025 10:35:32 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 586AZV37018165 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 6 Sep 2025 10:35:31 GMT Received: from hu-mchunara-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Sat, 6 Sep 2025 03:35:27 -0700 Date: Sat, 6 Sep 2025 16:05:16 +0530 From: Monish Chunara To: Konrad Dybcio CC: Dmitry Baryshkov , Wasim Nazir , Ulf Hansson , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Bjorn Andersson , "Konrad Dybcio" , Richard Cochran , , , , , , Subject: Re: [PATCH 2/5] arm64: dts: qcom: lemans: Add SDHC controller and SDC pin configuration Message-ID: References: <3b691f3a-633c-4a7f-bc38-a9c464d83fe1@oss.qualcomm.com> <57ae28ea-85fd-4f8b-8e74-1efba33f0cd2@oss.qualcomm.com> <53aac104-76fb-42b8-9e0d-0e8a3f59b2da@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: wo8qEMHwPp8nK8HAoRaGs2-BQ7c28M5g X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAwNCBTYWx0ZWRfX38zelVu8tA0t J/V//XuPDhFnR8ob789BhaeY/2qB/Ila1PVzFd/oZ5lnqWS5egVMolY6wljHEVYfF12zpCyKZhQ l/RbaoFiqifh5vABzgFErJwloRzTp9I7FLNrcVoflCjH0flzmg+F1ZRlI/5ksup12H9bWPEvQ03 grkof3mIOjuqEWh6uu+g+nT87xS2q+Dk+d1xNeP7oSG5aGrfG3eR7to9DZ4AIoUzcmlzTWgQ6es fDIBwEOnsBtfgt47GTvJishrGwh99/7Ht04ZlfVW10Zn+LpPSAYZelJ8/V6+4iIM6hvdU9aQWkH /0R3uBBQkqJO+wF3yfcFyUsOreHkMODk2Cl4PwkUvMZIeow3iIMVI/AXycr9NMiFAQesg7HPTJe h5/7A+IR X-Proofpoint-GUID: wo8qEMHwPp8nK8HAoRaGs2-BQ7c28M5g X-Authority-Analysis: v=2.4 cv=CaoI5Krl c=1 sm=1 tr=0 ts=68bc0e74 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=jXrvpXCBLM6H2ZY3dOMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-06_03,2025-09-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 clxscore=1015 malwarescore=0 adultscore=0 impostorscore=0 phishscore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060004 On Sat, Sep 06, 2025 at 10:28:47AM +0200, Konrad Dybcio wrote: > On 9/5/25 3:44 PM, Dmitry Baryshkov wrote: > > On Fri, Sep 05, 2025 at 02:04:47PM +0200, Konrad Dybcio wrote: > >> On 9/5/25 1:45 PM, Dmitry Baryshkov wrote: > >>> On Fri, Sep 05, 2025 at 01:14:29PM +0200, Konrad Dybcio wrote: > >>>> On 9/4/25 7:32 PM, Dmitry Baryshkov wrote: > >>>>> On Thu, Sep 04, 2025 at 04:34:05PM +0200, Konrad Dybcio wrote: > >>>>>> On 9/4/25 3:35 PM, Dmitry Baryshkov wrote: > >>>>>>> On Wed, Sep 03, 2025 at 09:58:33PM +0530, Wasim Nazir wrote: > >>>>>>>> On Wed, Sep 03, 2025 at 06:12:59PM +0200, Konrad Dybcio wrote: > >>>>>>>>> On 8/27/25 3:20 AM, Dmitry Baryshkov wrote: > >>>>>>>>>> On Tue, Aug 26, 2025 at 11:51:01PM +0530, Wasim Nazir wrote: > >>>>>>>>>>> From: Monish Chunara > >>>>>>>>>>> > >>>>>>>>>>> Introduce the SDHC v5 controller node for the Lemans platform. > >>>>>>>>>>> This controller supports either eMMC or SD-card, but only one > >>>>>>>>>>> can be active at a time. SD-card is the preferred configuration > >>>>>>>>>>> on Lemans targets, so describe this controller. > >>>>>>>>>>> > >>>>>>>>>>> Define the SDC interface pins including clk, cmd, and data lines > >>>>>>>>>>> to enable proper communication with the SDHC controller. > >>>>>>>>>>> > >>>>>>>>>>> Signed-off-by: Monish Chunara > >>>>>>>>>>> Co-developed-by: Wasim Nazir > >>>>>>>>>>> Signed-off-by: Wasim Nazir > >>>>>>>>>>> --- > >>>>>>>>>>> arch/arm64/boot/dts/qcom/lemans.dtsi | 70 ++++++++++++++++++++++++++++++++++++ > >>>>>>>>>>> 1 file changed, 70 insertions(+) > >>>>>>>>>>> > >>>>>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi > >>>>>>>>>>> index 99a566b42ef2..a5a3cdba47f3 100644 > >>>>>>>>>>> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi > >>>>>>>>>>> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi > >>>>>>>>>>> @@ -3834,6 +3834,36 @@ apss_tpdm2_out: endpoint { > >>>>>>>>>>> }; > >>>>>>>>>>> }; > >>>>>>>>>>> > >>>>>>>>>>> + sdhc: mmc@87c4000 { > >>>>>>>>>>> + compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5"; > >>>>>>>>>>> + reg = <0x0 0x087c4000 0x0 0x1000>; > >>>>>>>>>>> + > >>>>>>>>>>> + interrupts = , > >>>>>>>>>>> + ; > >>>>>>>>>>> + interrupt-names = "hc_irq", "pwr_irq"; > >>>>>>>>>>> + > >>>>>>>>>>> + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > >>>>>>>>>>> + <&gcc GCC_SDCC1_APPS_CLK>; > >>>>>>>>>>> + clock-names = "iface", "core"; > >>>>>>>>>>> + > >>>>>>>>>>> + interconnects = <&aggre1_noc MASTER_SDC 0 &mc_virt SLAVE_EBI1 0>, > >>>>>>>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDC1 0>; > >>>>>>>>>>> + interconnect-names = "sdhc-ddr", "cpu-sdhc"; > >>>>>>>>>>> + > >>>>>>>>>>> + iommus = <&apps_smmu 0x0 0x0>; > >>>>>>>>>>> + dma-coherent; > >>>>>>>>>>> + > >>>>>>>>>>> + resets = <&gcc GCC_SDCC1_BCR>; > >>>>>>>>>>> + > >>>>>>>>>>> + no-sdio; > >>>>>>>>>>> + no-mmc; > >>>>>>>>>>> + bus-width = <4>; > >>>>>>>>>> > >>>>>>>>>> This is the board configuration, it should be defined in the EVK DTS. > >>>>>>>>> > >>>>>>>>> Unless the controller is actually incapable of doing non-SDCards > >>>>>>>>> > >>>>>>>>> But from the limited information I can find, this one should be able > >>>>>>>>> to do both > >>>>>>>>> > >>>>>>>> > >>>>>>>> It’s doable, but the bus width differs when this controller is used for > >>>>>>>> eMMC, which is supported on the Mezz board. So, it’s cleaner to define > >>>>>>>> only what’s needed for each specific usecase on the board. > >>>>>>> > >>>>>>> `git grep no-sdio arch/arm64/boot/dts/qcom/` shows that we have those > >>>>>>> properties inside the board DT. I don't see a reason to deviate. > >>>>>> > >>>>>> Just to make sure we're clear > >>>>>> > >>>>>> I want the author to keep bus-width in SoC dt and move the other > >>>>>> properties to the board dt > >>>>> > >>>>> I think bus-width is also a property of the board. In the end, it's a > >>>>> question of schematics whether we route 1 wire or all 4 wires. git-log > >>>>> shows that bus-width is being sent in both files (and probalby we should > >>>>> sort that out). > >>>> > >>>> Actually this is the controller capability, so if it can do 8, it should > >>>> be 8 and the MMC core will do whatever it pleases (the not-super-sure > >>>> docs that I have say 8 for this platform) > >>> > >>> Isn't it a physical width of the bus between the controller and the slot > >>> or eMMC chip? > >> > >> No, that's matched against reported (sd/mmc) card capabilities IIUC > > > > What if both host and the card support 4 bits bus (normal SD card), but > > board has only one data wire? > > Ohhh, touche.. I assumed it's "smart" like PCIe, but it's (probably) > not. > > Sorry for the trouble, Wasim. Let's keep 4 for now and get this patch > merged. > > Konrad> Thanks for the discussion Dmitry and Konrad. This has been confirmed with hardware team as well that only 4 lines have been routed from the controller to the SD card slot on the board, as per the card specifications. We'll keep the value 4 in the board DTS as per the discussion. Best Regards, Monish