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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5608acfd2ffsm2500187e87.107.2025.09.06.12.24.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Sep 2025 12:24:56 -0700 (PDT) Date: Sat, 6 Sep 2025 22:24:54 +0300 From: Dmitry Baryshkov To: Sebastian Reichel Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Frank Wang , Zhang Yubing , Andy Yan , Maud Spierings , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC 1/2] dt-bindings: phy: rockchip-usbdp: add improved ports scheme Message-ID: References: <20250904-rock5b-dp-alt-mode-v1-0-23df726b31ce@collabora.com> <20250904-rock5b-dp-alt-mode-v1-1-23df726b31ce@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250904-rock5b-dp-alt-mode-v1-1-23df726b31ce@collabora.com> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAzMSBTYWx0ZWRfX0lNwL6Z0DyN4 3UlJE3PF93qx6PtZetHA0vyRagV5dDjFEudVEYHbc7LsMHHZI/cx/zuHyBzVXi2CpW5sF0q6phQ XFhvG/5edjwack8EusIl+YwJPZMMBbTEU3OCMWKhTZxQRCMp4FlFGTV+lK4lHZxD4DLhlapl7B2 HJtL5dmAhahax02UuUd1Z65/OT66f81sKhX4Y+zgW9CGVcbgeEb+VVztVZf9r94aJMEXA3vhK52 VkiGCdFauRibYj85I4dPyQ4I4N918qPHBD16S2hPOBy4nG5KNUkDzfOCdW+l0TeU38T93NLt7KM A0786zIM+9BTwztQ8TTYrwmA4gZ3T84d+RullZpampf3yGNXtrOvBnTWKKC9y/a4IwQrQojYqWU zec8Zuvi X-Proofpoint-ORIG-GUID: 0cejpn5SObRV5_A-oVY3ies9vCpplP0n X-Proofpoint-GUID: 0cejpn5SObRV5_A-oVY3ies9vCpplP0n X-Authority-Analysis: v=2.4 cv=VIDdn8PX c=1 sm=1 tr=0 ts=68bc8a8a cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=xqWC_Br6kY4A:10 a=kj9zAlcOel0A:10 a=yJojWOMRYYMA:10 a=JfrnYn6hAAAA:8 a=QX4gbG5DAAAA:8 a=OfM26ny4dbP1suOavW4A:9 a=CjuIK1q_8ugA:10 a=1HOtulTD9v-eNWfpl4qZ:22 a=1CNFftbPRP8L7MoqJWF3:22 a=AbAUZ8qAyYyZVLSsDulk:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-06_07,2025-09-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 spamscore=0 suspectscore=0 bulkscore=0 phishscore=0 adultscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060031 On Thu, Sep 04, 2025 at 08:26:02PM +0200, Sebastian Reichel wrote: > Currently the Rockchip USBDP PHY as a very simply port scheme: It just > offers a single port, which is supposed to point towards the connector. > Usually with 2 endpoints, one for the USB-C superspeed port and one for > the USB-C SBU port. > > This scheme is not good enough to properly handle DP AltMode, so add > a new scheme, which has separate ports for everything. This has been > modelled after the Qualcomm QMP USB4-USB3-DP PHY controller binding > with a slight difference that there is an additional port for the > USB-C SBU port as the Rockchip USB-DP PHY also contains the mux. > > Signed-off-by: Sebastian Reichel > --- > .../bindings/phy/phy-rockchip-usbdp.yaml | 23 ++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml > index 8b7059d5b1826fdec5170cf78d6e27f2bd6766bb..f728acf057e4046a4d254ee687af3451f17bcd01 100644 > --- a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml > +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml > @@ -114,6 +114,29 @@ properties: > A port node to link the PHY to a TypeC controller for the purpose of > handling orientation switching. > > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of the PHY for USB (or DP when configured into 4 lane > + mode), which should point to the superspeed port of a USB connector. What abourt USB+DP mode, where each one gets 2 lanes? > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: Incoming endpoint from the USB controller > + > + port@2: > + $ref: /schemas/graph.yaml#/properties/port > + description: Incoming endpoint from the DisplayPort controller > + > + port@3: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of the PHY for DP, which should either point to the > + SBU port of a USB-C connector or a DisplayPort connector input port. I would suggest describing this port as 'DisplayPort AUX signals to be connected to the SBU port of a USB-C connector (maybe through the additinal mux, switch or retimer)'. It should not be confused with the actual DisplayPort signals (as those go through the port@0). In the Qualcomm world we currently do not describe this link from the PHY to the gpio-mux or retimer, but I think we will have to do that soon. > + > required: > - compatible > - reg > > -- > 2.50.1 > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip -- With best wishes Dmitry