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From: "Sun, Yi" <yi.sun@intel.com>
To: Vinod Koul <vkoul@kernel.org>
Cc: "Gomes, Vinicius" <vinicius.gomes@intel.com>,
	"Jiang, Dave" <dave.jiang@intel.com>,
	"dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"Jin, Gordon" <gordon.jin@intel.com>,
	"fenghuay@nvidia.com" <fenghuay@nvidia.com>,
	"Lai, Yi1" <yi1.lai@intel.com>
Subject: Re: [PATCH v3 1/2] dmaengine: idxd: Expose DSA3.0 capabilities through sysfs
Date: Sat, 13 Sep 2025 16:50:47 +0800	[thread overview]
Message-ID: <aMUwZ30sz9IU0gEO@ysun46-mobl.ccr.corp.intel.com> (raw)
In-Reply-To: <DS0PR11MB637482C854F7C5FF32033D8F9906A@DS0PR11MB6374.namprd11.prod.outlook.com>

Hi Vinod,

Gentle ping —— if splitting into three sysfs entries is really required, please let me know so I can adjust in time and avoid missing the v6.17 merge window.

Thanks
    --Sun, Yi

On 02.09.2025 16:34, Sun, Yi wrote:
>Hi Vinod,
>
>The three capability registers are consecutive in BAR0 (0x180, 0x188, 0x190) and represent a single functionality. Exposing them as one sysfs entry makes their relationship clearer and avoids clutter, since there are already many files under dsa<x>.
>
>If more capability registers are added at sequential offsets and for the same function in the future, they can be appended in order(higher offsets placed left-to-right) to maintain consistency.
>
>We considered exposing them as separate files, but agreed that a single file provides better clarity and reduces noise.
>
>Thanks
>   --Sun, Yi
>
>-----Original Message-----
>From: Vinod Koul <vkoul@kernel.org>
>Sent: Tuesday, September 2, 2025 15:25
>To: Sun, Yi <yi.sun@intel.com>
>Cc: Gomes, Vinicius <vinicius.gomes@intel.com>; Jiang, Dave <dave.jiang@intel.com>; dmaengine@vger.kernel.org; linux-kernel@vger.kernel.org; Jin, Gordon <gordon.jin@intel.com>; fenghuay@nvidia.com; Lai, Yi1 <yi1.lai@intel.com>; Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
>Subject: Re: [PATCH v3 1/2] dmaengine: idxd: Expose DSA3.0 capabilities through sysfs
>
>On 21-08-25, 16:51, Yi Sun wrote:
>> Introduce sysfs interfaces for 3 new Data Streaming Accelerator (DSA)
>> capability registers (dsacap0-2) to enable userspace awareness of hardware
>> features in DSA version 3 and later devices.
>>
>> Userspace components (e.g. configure libraries, workload Apps) require this
>> information to:
>> 1. Select optimal data transfer strategies based on SGL capabilities
>> 2. Enable hardware-specific optimizations for floating-point operations
>> 3. Configure memory operations with proper numerical handling
>> 4. Verify compute operation compatibility before submitting jobs
>>
>> The output format is <dsacap2>,<dsacap1>,<dsacap0>, where each DSA
>> capability value is a 64-bit hexadecimal number, separated by commas.
>> The ordering follows the DSA 3.0 specification layout:
>>  Offset:    0x190    0x188    0x180
>>  Reg:       dsacap2  dsacap1  dsacap0
>>
>> Example:
>> cat /sys/bus/dsa/devices/dsa0/dsacaps
>>  000000000000f18d,0014000e000007aa,00fa01ff01ff03ff
>
>sysfs are supposed to be single values only, should we rather do per
>capability? Also in future if you have more than three...? what happens
>then?
>
>-- 
>~Vinod

  reply	other threads:[~2025-09-13  8:51 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-21  8:51 [PATCH v3 0/2] dmaengine: idxd: Add basic DSA 3.0 capability and SGL support Yi Sun
2025-08-21  8:51 ` [PATCH v3 1/2] dmaengine: idxd: Expose DSA3.0 capabilities through sysfs Yi Sun
2025-09-02  7:25   ` Vinod Koul
2025-09-02  8:34     ` Sun, Yi
2025-09-13  8:50       ` Sun, Yi [this message]
2025-08-21  8:51 ` [PATCH v3 2/2] dmaengine: idxd: Add Max SGL Size Support for DSA3.0 Yi Sun

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