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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?cXKiEiJeBlZ0HH1ACEMzRmOEqM27SgmSQyHWvX7wQeESscxDyqBKzJWvdtT3?= =?us-ascii?Q?M9i9zrUh5n61yMOJCDqDdCvpYrYlUF7SVc041+SctyQd+MmY53aLwrImW11z?= =?us-ascii?Q?b9bHH0vtMkrv5KOfPEIc7dpMbFJOiZDG1m3ljLVA6Q9YKlnphLCzOhtu/yh3?= =?us-ascii?Q?DHI8lY41HQuReeDiVE9a5B9+9qG4K9+xC998ySfp/y5Sm8MKnNQzGMqC8m3o?= =?us-ascii?Q?ZUzoCQ/4f7zP4zEQu9n13fD25WuMjxEEmRIvh/QAwisgOEG/g+2m+f519i/v?= =?us-ascii?Q?ghYZXgYItKUJXkRHcMWdBh3KiKgu0tKnsj3JyAF5nQPquoiSVDZ6js2PITju?= =?us-ascii?Q?e57WxzzKxMb2FiOtDPm/n4w3uzZdtFIh3GjDpNlEOJicZXEK73DSTS1gtEmo?= =?us-ascii?Q?8PmSQXQ0W28Iz1blnSivz00Gn9c0lDewv0Op/CAlBiKh8LGfaYi7X8fB8ov2?= =?us-ascii?Q?RiayZSF2buI+TpFlhzFdXXyrPQttVGshTqm5nHFYS+NNQ9atqOnQV9tbWA3g?= =?us-ascii?Q?YH3kuccUOgESMOazvrY+a44ZzJc4zXlQ2kLNn9e+tHnapm6Xmc8EmdCAvrPv?= =?us-ascii?Q?q4DfTc//NEZPG7fupkRMXOR7LwQv6Jo6gHuaJCAW3kxd78XQbuZTDRz0MrSn?= =?us-ascii?Q?nlRnVeZ6SqUJFSCyO2twQGkzLt4GDENMW7acLWT/bmQxRG4eGxcckfkOnrTG?= =?us-ascii?Q?Jlfgj3iqgre2gzSR7cFUTvUGAyE4RByOkAw5sf01RHqvV7zTOhAYuEeXxxS0?= =?us-ascii?Q?iOhEmELUtwi1ATZ+PaWeTXGUrQfNCyxcaEgj7tQtqL4bi1eVp7kFlyH8l/FI?= =?us-ascii?Q?RRT5F14ylmkKkZtaQGghSGXxcHxZGBhcv6/kR5nq59ZvWO1Ea1pTUhLrqfD+?= =?us-ascii?Q?LyMAJOz023jAwVHCuwI9jGu2DnRalXBvCqMlHDNKjwDcNQBRBMINl4S3UJup?= =?us-ascii?Q?Au5X/Wr5ijnEE0F/tTqEwiYPaE7up02Y6oJ6ZvaHt70e+Nr+9U94RmZRTxd2?= =?us-ascii?Q?jOoaOAVAlw3et14f6A7r3yASXgbNqAaPd5jNiOHNO2L1HEhpD4a1gtWoKhZG?= =?us-ascii?Q?zBLNAnAtvpYRg4yyW/UR2twzjXPIbcQ8jZTvPIvf5WNOKGSwhn31CP2xYrRf?= =?us-ascii?Q?rIGUrCA80xTM0A9QB2zkBbiPX4/gik2aBr+TjYdXcjPohzUoT6Y3+bbqdN7a?= =?us-ascii?Q?RSWMF4sdvwSlNWNc+R97OoFXdApooUMti4nuwGYzQ7jhwVEfHvxinZHBvZdr?= =?us-ascii?Q?sZD9GlNq6KybZOgSv4qZlQ7kU/5fQc2XjYj6OPSWn5g7DLW6+fPoAIySq12x?= =?us-ascii?Q?crpYpLeCqspnzLcfNyhEB+cLvJTioI4Oh/ZHGBk2S3ogDDn43qg2sdt66XkN?= =?us-ascii?Q?7oB5rRA67th74gEw/to3+OSrBzxoq2e56dHUoWvI4ChpMD7rzVZmq2l+j/TH?= =?us-ascii?Q?HBmXu1aw4k6ewgEiauyHg94xNrUjAh1y2oSNmhRctyOnBn0/1lzwWdA6JRTI?= =?us-ascii?Q?1sMWtoesDLmGWMLtgImVyVeRMl5AFDjUrg+lQcfgx3K9TYj6VBMbLu/EqC3X?= =?us-ascii?Q?v4qlHp+APIG/VVSYnWB9BWeVkvAUvGpzXcaposmN?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0f06b881-4e94-4869-1ef9-08ddf606bcb6 X-MS-Exchange-CrossTenant-AuthSource: PAXSPRMB0053.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Sep 2025 16:24:55.4022 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: HFKizqBNJjoxz5lSZBUcTRLcx2PhbmtTpcvNWEyj3He2XhZK5zy2erRPx6s/H5773Jc5oEA6pvcOFAAnvvS95g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB9859 On Wed, Sep 17, 2025 at 03:27:06PM +0800, Haibo Chen wrote: > Extract function nxp_fspi_dll_override(), this is the suggested setting > when clock rate < 100MHz. Just the preparation of supportting DTR mode. Remove "this is the suggested setting when clock rate < 100MHz", which is not related this patch. Extract nxp_fspi_dll_override() for preparation of DTR mode support. Reviewed-by: Frank Li > > Signed-off-by: Haibo Chen > --- > drivers/spi/spi-nxp-fspi.c | 19 ++++++++++++------- > 1 file changed, 12 insertions(+), 7 deletions(-) > > diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c > index 848fa9319e36d65e8152931324b8e34eb162f5d3..db4b92490de957580c6298baeb8b68a310c23615 100644 > --- a/drivers/spi/spi-nxp-fspi.c > +++ b/drivers/spi/spi-nxp-fspi.c > @@ -674,6 +674,17 @@ static void nxp_fspi_dll_calibration(struct nxp_fspi *f) > dev_warn(f->dev, "DLL lock failed, please fix it!\n"); > } > > +/* > + * Config the DLL register to default value, enable the target clock delay > + * line delay cell override mode, and use 1 fixed delay cell in DLL delay > + * chain, this is the suggested setting when clock rate < 100MHz. > + */ > +static void nxp_fspi_dll_override(struct nxp_fspi *f) > +{ > + fspi_writel(f, FSPI_DLLACR_OVRDEN, f->iobase + FSPI_DLLACR); > + fspi_writel(f, FSPI_DLLBCR_OVRDEN, f->iobase + FSPI_DLLBCR); > +} > + > /* > * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0 > * register and start base address of the target device. > @@ -1071,13 +1082,7 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f) > /* Disable the module */ > fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0); > > - /* > - * Config the DLL register to default value, enable the target clock delay > - * line delay cell override mode, and use 1 fixed delay cell in DLL delay > - * chain, this is the suggested setting when clock rate < 100MHz. > - */ > - fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR); > - fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR); > + nxp_fspi_dll_override(f); > > /* enable module */ > fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | > > -- > 2.34.1 >