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[50.32.2.77]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-8a46b2f3cdasm503126939f.4.2025.09.22.20.29.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 20:29:09 -0700 (PDT) Date: Mon, 22 Sep 2025 23:29:07 -0400 From: Gregory Price To: Terry Bowman Cc: dave@stgolabs.net, jonathan.cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, dan.j.williams@intel.com, bhelgaas@google.com, shiju.jose@huawei.com, ming.li@zohomail.com, Smita.KoralahalliChannabasappa@amd.com, rrichter@amd.com, dan.carpenter@linaro.org, PradeepVineshReddy.Kodamati@amd.com, lukas@wunner.de, Benjamin.Cheatham@amd.com, sathyanarayanan.kuppuswamy@linux.intel.com, linux-cxl@vger.kernel.org, alucerop@amd.com, ira.weiny@intel.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v11 00/23] Enable CXL PCIe Port Protocol Error handling and logging Message-ID: References: <20250827013539.903682-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250827013539.903682-1-terry.bowman@amd.com> On Tue, Aug 26, 2025 at 08:35:15PM -0500, Terry Bowman wrote: > This patchset adds CXL Protocol Error handling for CXL Ports and updates CXL > Endpoints (EP) handling. Previous versions of this series can be found here: > https://lore.kernel.org/linux-cxl/20250626224252.1415009-1-terry.bowman@amd.com/ > I know there's still some in-flight work, but for the series so far: Tested-by: Gregory Price Please ping me if major logical rework gets done and i'll roll through it again.