From: Alison Schofield <alison.schofield@intel.com>
To: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>
Cc: <linux-cxl@vger.kernel.org>, Davidlohr Bueso <dave@stgolabs.net>,
"Jonathan Cameron" <jonathan.cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
"Dan Williams" <dan.j.williams@intel.com>,
Jonathan Corbet <corbet@lwn.net>, <linux-doc@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, Gregory Price <gourry@gourry.net>,
Robert Richter <rrichter@amd.com>,
Cheatham Benjamin <benjamin.cheatham@amd.com>
Subject: Re: [PATCH 4/4 v5] cxl/test: Simulate an x86 Low Memory Hole for tests
Date: Wed, 8 Oct 2025 20:52:07 -0700 [thread overview]
Message-ID: <aOcxZ1ju0FmB5Xi7@aschofie-mobl2.lan> (raw)
In-Reply-To: <20251006155836.791418-5-fabio.m.de.francesco@linux.intel.com>
On Mon, Oct 06, 2025 at 05:58:07PM +0200, Fabio M. De Francesco wrote:
> Simulate an x86 Low Memory Hole for the CXL tests by changing the first
> mock CFMWS range size to 768MB and the CXL Endpoint Decoder HPA range
> sizes to 1GB. The auto-created region of cxl-test uses mock_cfmws[0],
> therefore the LMH path in the CXL Driver will be exercised every time
> the cxl-test module is loaded.
>
> Since mock_cfmws[0] range base address is typically different from the
> one published by the BIOS on real hardware, the driver would fail to
> create and attach CXL Regions when it's run on the mock environment
> created by cxl-tests. Furthermore, cxl-topology.sh, cxl-events.sh, and
> cxl-sanitize.sh, would also fail.
>
> To make the above-mentioned tests succeed again, add two "mock" versions
> of platform_*() that check the HPA range start of mock_cfmws[0] instead
> of LMH_CFMWS_RANGE_START. When cxl_core calls a cxl_core exported
> function and that function is mocked by cxl_test, the call chain causes
> a circular dependency issue. Then add also two "redirect" versions of
> platform_*() to work out the circular dependency issue.
This is some amazing mockness here !!!!
Please make it easier to review and maintain by making these 2 mock
functions match their core counterparts exactly with only one exception:
s/LMH_CFMWS_RANGE_START/mock_cfmws0_range_start
Doable, right?
>
> +static bool
> +mock_platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd,
> + const struct cxl_endpoint_decoder *cxled)
> +{
> + const struct range *rd_r, *ed_r;
> + int align;
> +
> + rd_r = &cxlrd->cxlsd.cxld.hpa_range;
> + ed_r = &cxled->cxld.hpa_range;
> + align = cxled->cxld.interleave_ways * SZ_256M;
> +
> + return rd_r->start == mock_cfmws0_range_start &&
> + rd_r->start == ed_r->start &&
> + rd_r->end < (mock_cfmws0_range_start + SZ_4G) &&
> + rd_r->end < ed_r->end &&
> + IS_ALIGNED(range_len(ed_r), align);
> +}
> +
> +static bool
> +mock_platform_region_matches_cxld(const struct cxl_region_params *p,
> + const struct cxl_decoder *cxld)
> +{
> + const struct range *r = &cxld->hpa_range;
> + const struct resource *res = p->res;
> + int align = cxld->interleave_ways * SZ_256M;
> +
> + return res->start == mock_cfmws0_range_start &&
> + res->start == r->start &&
> + res->end < (mock_cfmws0_range_start + SZ_4G) &&
> + res->end < r->end &&
> + IS_ALIGNED(range_len(r), align);
> +}
> +
>
prev parent reply other threads:[~2025-10-09 3:52 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-06 15:58 [PATCH 0/4 v5] cxl/core: Enable Region creation/attach on x86 with LMH Fabio M. De Francesco
2025-10-06 15:58 ` [PATCH 1/4 v5] cxl/core: Change match_*_by_range() signatures Fabio M. De Francesco
2025-10-06 17:35 ` Gregory Price
2025-10-06 23:30 ` Dave Jiang
2025-10-06 15:58 ` [PATCH 2/4 v5] cxl/core: Add helpers to detect Low Memory Holes on x86 Fabio M. De Francesco
2025-10-06 17:40 ` Gregory Price
2025-10-07 0:00 ` Dave Jiang
2025-10-09 3:16 ` Alison Schofield
2025-11-05 18:02 ` Fabio M. De Francesco
2025-10-10 7:38 ` kernel test robot
2025-11-05 18:11 ` Fabio M. De Francesco
2025-10-10 14:49 ` kernel test robot
2025-11-05 18:20 ` Fabio M. De Francesco
2025-11-05 18:51 ` Dave Jiang
2025-10-28 15:58 ` Jonathan Cameron
2025-10-06 15:58 ` [PATCH 3/4 v5] cxl/core: Enable Region creation on x86 with LMH Fabio M. De Francesco
2025-10-06 17:46 ` Gregory Price
2025-10-07 20:25 ` Dave Jiang
2025-10-09 14:30 ` Gregory Price
2025-10-09 3:29 ` Alison Schofield
2025-10-06 15:58 ` [PATCH 4/4 v5] cxl/test: Simulate an x86 Low Memory Hole for tests Fabio M. De Francesco
2025-10-07 20:37 ` Dave Jiang
2025-10-09 3:34 ` Alison Schofield
2025-10-09 3:52 ` Alison Schofield [this message]
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