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Fri, 07 Nov 2025 05:51:58 -0800 (PST) Received: from hu-nlaad-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29651cc6595sm61506885ad.98.2025.11.07.05.51.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Nov 2025 05:51:57 -0800 (PST) Date: Fri, 7 Nov 2025 19:21:51 +0530 From: Nilesh Laad To: Dmitry Baryshkov Cc: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, venkata.valluru@oss.qualcomm.com, jessica.zhang@oss.qualcomm.com, Yi Zhang Subject: Re: [PATCH] drm/bridge: add support for lontium lt9211c bridge Message-ID: References: <20250911-lt9211c-bridge-support-v1-1-c221202cbcd5@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTA3MDExNCBTYWx0ZWRfX0k9u67dXK7K/ 8X4fsTF4HRg+49DpVvR4126IfVXVIeGmcgbZI+NV533vlEmhgt5ibs4/QylQ0DFJjaos4i/0UmR Ja4Lu/b6095w49Uk0gkf0vzJobPAwk2Sex1AiAcs8RBTTH5OFEgf4JQR/tKVIAIyOYGsjNcJ+m8 GNbK1OMJqYwhebb/feSv9lS4++lY6QUNPFCu70o57B3y7b8YOaqOo+PNBQETIs8FNg9LGPx2Vo/ pYKwK/IBh7YFRkwWi8MmCOEHDHQB4dRekUSNx4M5hq1zLda2e+OpT4rQPAmILCpkGOiJbyaXlEq 5Ooh0qxjTh00qM2OCDrvDdE69FQGmrVvnooa36AS/0mvSsvl4waFYAA9MxmiUvIRD/2WbcXNUZH gd8RXgmZhvk1vfaKEEfoFkAQKqk5bA== X-Authority-Analysis: v=2.4 cv=Csmys34D c=1 sm=1 tr=0 ts=690df980 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=kj9zAlcOel0A:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=h0J1ii3O1rLK1nQplmoA:9 a=CjuIK1q_8ugA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: kMi0iCsHnDatEwohc-TYslPj8Vwu3OsT X-Proofpoint-ORIG-GUID: kMi0iCsHnDatEwohc-TYslPj8Vwu3OsT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-07_03,2025-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511070114 On Mon, Sep 15, 2025 at 04:19:57AM +0300, Dmitry Baryshkov wrote: > On Thu, Sep 11, 2025 at 08:25:27PM +0530, Nilesh Laad wrote: > > From: Yi Zhang > > > > LT9211c is a Single/Dual-Link DSI/LVDS or Single DPI input to > > Single-link/Dual-Link DSI/LVDS or Single DPI output bridge chip. > > Add support for DSI to LVDS bridge configuration. > > > > Signed-off-by: Yi Zhang > > Signed-off-by: Nilesh Laad > > Please send the driver together with the bindings, in one series. Addressed in https://lore.kernel.org/lkml/20251107-add-lt9211c-bridge-v2-0-b0616e23407c@oss.qualcomm.com/ > > The driver looks pretty similar to the existing LT9211 driver. Please > explain why you can't extend that one. LT9211 and LT9211C differ completely in register programming sequences. Even lontium mentioned that register configuration are different for lt9211 and lt9211c. Nearly every function would require duplicated logic with if (chip_type) branching, as register sequence are completely different. Having both sequences in single file is not looking good, hence want to merge as separate driver. > > > --- > > drivers/gpu/drm/bridge/Kconfig | 13 + > > drivers/gpu/drm/bridge/Makefile | 1 + > > drivers/gpu/drm/bridge/lontium-lt9211c.c | 1105 ++++++++++++++++++++++++++++++ > > 3 files changed, 1119 insertions(+) > > > > + const struct reg_sequence lt9211c_tx_ssc_seq[] = { > > + { 0x8234, 0x00 }, > > + { 0x856e, 0x10 }, > > + { 0x8181, 0x15 }, > > + { 0x871e, 0x00 }, > > + { 0x8717, 0x02 }, > > + { 0x8718, 0x04 }, > > + { 0x8719, 0xd4 }, > > + { 0x871A, 0x00 }, > > + { 0x871B, 0x12 }, > > + { 0x871C, 0x00 }, > > + { 0x871D, 0x24 }, > > + { 0x871F, 0x1c }, > > lowercase the hex, please. > > > + { 0x8720, 0x00 }, > > + { 0x8721, 0x00 }, > > + { 0x871e, 0x02 }, > > + }; > > + > > [...] > > > + > > +static void lt9211c_atomic_enable(struct drm_bridge *bridge, > > + struct drm_atomic_state *state) > > +{ > > + struct lt9211c *ctx = bridge_to_lt9211c(bridge); > > + const struct drm_bridge_state *bridge_state; > > + const struct drm_crtc_state *crtc_state; > > + struct drm_connector *connector; > > + struct drm_crtc *crtc; > > + u32 bus_flags; > > + int ret; > > + > > + ret = regulator_enable(ctx->vccio); > > + if (ret) { > > + dev_err(ctx->dev, "Failed to enable vccio: %d\n", ret); > > + return; > > + } > > + > > + /* Deassert reset */ > > + gpiod_set_value(ctx->reset_gpio, 1); > > + usleep_range(20000, 21000); /* Very long post-reset delay. */ > > + > > + /* Get the LVDS format from the bridge state. */ > > + bridge_state = drm_atomic_get_new_bridge_state(state, bridge); > > + bus_flags = bridge_state->output_bus_cfg.flags; > > + ctx->de = !!(bus_flags & DRM_BUS_FLAG_DE_HIGH); > > + > > + switch (bridge_state->output_bus_cfg.format) { > > + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: > > + ctx->bpp24 = false; > > + ctx->jeida = true; > > + break; > > + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: > > + ctx->bpp24 = true; > > + ctx->jeida = true; > > + break; > > + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: > > + ctx->bpp24 = true; > > + ctx->jeida = false; > > + break; > > + default: > > + /* > > + * Some bridges still don't set the correct > > + * LVDS bus format, use SPWG24 default > > + * format until those are fixed. > > + */ > > + ctx->bpp24 = true; > > + ctx->jeida = false; > > + dev_warn(ctx->dev, > > + "Unsupported LVDS bus format 0x%04x\n", > > + bridge_state->output_bus_cfg.format); > > + break; > > + } > > + > > + /* > > + * Retrieve the CRTC adjusted mode. This requires a little dance to go > > + * from the bridge to the encoder, to the connector and to the CRTC. > > + */ > > + connector = drm_atomic_get_new_connector_for_encoder(state, > > + bridge->encoder); > > + crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; > > + crtc_state = drm_atomic_get_new_crtc_state(state, crtc); > > + drm_mode_copy(&ctx->mode, &crtc_state->adjusted_mode); > > + > > + dev_dbg(ctx->dev, "width=%d,height=%d,clock=%d\n", > > + ctx->mode.hdisplay, > > + ctx->mode.vdisplay, > > + ctx->mode.clock); > > + > > + ret = lt9211c_read_chipid(ctx); > > + if (ret) > > + return; > > + > > + /* Lt9211c must enable after mipi clock enable */ > > + queue_delayed_work(ctx->wq, &ctx->lt9211c_dw, > > + msecs_to_jiffies(100)); > > At this point MIPI clock should be enabled. > Yes, MIPI clock is enabled here but a delay is required for lt9211c to detect the mipi signals. Added queue_delayed_work() to defer execution without blocking main thread. > > + > > + dev_dbg(ctx->dev, "LT9211 enabled.\n"); > > +} > > + > > [...] > > > + > > +MODULE_DESCRIPTION("Lontium LT9211C DSI/LVDS/DPI bridge driver"); > > +MODULE_LICENSE("GPL"); > > Missing MODULE_AUTHOR > > > > > --- > > base-commit: f50b969bafafb2810a07f376387350c4c0d72a21 > > change-id: 20250911-lt9211c-bridge-support-9209f7cc7697 > > prerequisite-message-id: <20250910-add-lt9211c-bridge-v1-1-4f23740fe101@oss.qualcomm.com> > > prerequisite-patch-id: 79524a1aaba6b39f49603db725539cf11176820b > > > > Best regards, > > -- > > Nilesh Laad > > > > -- > With best wishes > Dmitry