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Thu, 20 Nov 2025 02:18:53 -0800 (PST) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7c3f0243b3csm2273910b3a.36.2025.11.20.02.18.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Nov 2025 02:18:53 -0800 (PST) Date: Thu, 20 Nov 2025 15:48:49 +0530 From: Abhinaba Rakshit To: Konrad Dybcio Cc: Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] soc: qcom: ice: Set ICE clk to turbo on probe Message-ID: References: <20251001-set-ice-clock-to-turbo-v1-1-7b802cf61dda@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-ORIG-GUID: L380p5KNVgaFxHDC-MUDFF3d5e8GDFPJ X-Proofpoint-GUID: L380p5KNVgaFxHDC-MUDFF3d5e8GDFPJ X-Authority-Analysis: v=2.4 cv=SJ5PlevH c=1 sm=1 tr=0 ts=691eeb0f cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=kj9zAlcOel0A:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=M7-gVhU5_WYnB0XQLAAA:9 a=CjuIK1q_8ugA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTIwMDA2MSBTYWx0ZWRfX+tV3zFLLj/BW ijqJumrOoMTdaRIKtZQy229qCM1OCYOmN6fnVg4grCoIuP7aagC99rrIZRS6coqN++SUt1//FTX CGVFNp08MqdhcpqVc19yVmpdjtc61HhMJ+JKyWvac23gunoF0b/0305cy5u9RpXbiGTAVCs/tT2 TViOllWT1QaVjYg6RIQOkKA1h4oiLMuJcQ8yjLzRRlGAhiSTf/VdPxWyHah03ukfFcmC4bDDDMN L7HZheKMS5daWRLKTI99aS5HmpMeMiIgiUqU3eUR3MemOO8rJJi4iD7hN3xU7o5E15oXLHcIJoy /3pJwTPp4JdOnymtrwhbTyn6QaqyT+JzPIJ693qKvk4bEaN17r3eRyYuVlpFERvr9eg/XTyhCEo eHucyXMlJDTnJTBOTNo+ApuzzxKYPw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-20_03,2025-11-20_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 adultscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511200061 On Thu, Oct 02, 2025 at 11:39:05AM +0200, Konrad Dybcio wrote: > On 10/1/25 2:14 PM, Abhinaba Rakshit wrote: > > Set ICE core clock to turbo (max freq) provided by dt > > entry at ice device probe. > > > > Signed-off-by: Abhinaba Rakshit > > --- > > MMC controller lacks a clock scaling mechanism, unlike the UFS > > controller. By default, the MMC controller is set to TURBO mode > > during probe, but the ICE clock remains at XO frequency, > > leading to read/write performance degradation on eMMC. > > > > To address this, set the ICE clock to TURBO during probe to > > align it with the controller clock. This ensures consistent > > performance and avoids mismatches between the controller > > and ICE clock frequencies. > > --- > > drivers/soc/qcom/ice.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c > > index ec8d6bb9f426deee1038616282176bfc8e5b9ec1..eee06c499dc36a6bf380361f27e938331f1fcb10 100644 > > --- a/drivers/soc/qcom/ice.c > > +++ b/drivers/soc/qcom/ice.c > > @@ -535,6 +535,7 @@ static struct qcom_ice *qcom_ice_create(struct device *dev, > > struct qcom_ice *engine; > > const __be32 *prop; > > int len; > > + int err; > > > > if (!qcom_scm_is_available()) > > return ERR_PTR(-EPROBE_DEFER); > > @@ -577,6 +578,13 @@ static struct qcom_ice *qcom_ice_create(struct device *dev, > > if (!qcom_ice_check_supported(engine)) > > return ERR_PTR(-EOPNOTSUPP); > > > > + /* Set the ICE clk rate to TURBO */ > > + if (engine->core_clk && engine->max_freq) { > > + err = clk_set_rate(engine->core_clk, engine->max_freq); > > Please make sure to use dev_pm_opp_set_rate() and add introduce an OPP > table to ensure that there's also a turbo rpm(h) vote to match.. > > Konrad Sure, will move the solution using OPP-table as suggested in patchset-v2.