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X-CSE-ConnectionGUID: FPaPhBe+RgmFqy57RWM24Q== X-CSE-MsgGUID: nLjgBoflSHa3848cDQSamQ== X-IronPort-AV: E=McAfee;i="6800,10657,11608"; a="75421180" X-IronPort-AV: E=Sophos;i="6.19,293,1754982000"; d="scan'208";a="75421180" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2025 00:43:48 -0800 X-CSE-ConnectionGUID: sNsYiFy4T+uyIn2RzpR7ZQ== X-CSE-MsgGUID: maDAue3fSwqWlY0B6+ZFow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,293,1754982000"; d="scan'208";a="188455479" Received: from pgcooper-mobl3.ger.corp.intel.com (HELO kekkonen.fi.intel.com) ([10.245.245.238]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2025 00:43:42 -0800 Received: from kekkonen.localdomain (localhost [IPv6:::1]) by kekkonen.fi.intel.com (Postfix) with SMTP id A55521205FC; Mon, 10 Nov 2025 10:43:41 +0200 (EET) Date: Mon, 10 Nov 2025 10:43:41 +0200 Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo From: Sakari Ailus To: Michael Riesch Cc: Laurent Pinchart , Mehdi Djait , Maxime Chevallier , =?iso-8859-1?Q?Th=E9o?= Lebrun , Thomas Petazzoni , Gerald Loacker , Bryan O'Donoghue , Markus Elfring , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Nicolas Dufresne , Sebastian Reichel , Collabora Kernel Team , Paul Kocialkowski , Alexander Shiyan , Val Packett , Rob Herring , Philipp Zabel , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Mehdi Djait , Krzysztof Kozlowski , Bryan O'Donoghue , Chen-Yu Tsai Subject: Re: [PATCH v14 00/18] media: rockchip: add a driver for the rockchip camera interface Message-ID: References: <20240220-rk3568-vicap-v14-0-b38b6da0fc80@collabora.com> <074cd08e-0412-49f9-8dd9-b1f96eb11717@collabora.com> <20251107185441.GG5558@pendragon.ideasonboard.com> <13c43edb-9592-4779-a39a-7856bb0f964d@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <13c43edb-9592-4779-a39a-7856bb0f964d@collabora.com> Hi Michael, Laurent, On Fri, Nov 07, 2025 at 09:51:37PM +0100, Michael Riesch wrote: > Hi Laurent, > > On 11/7/25 19:54, Laurent Pinchart wrote: > > On Fri, Nov 07, 2025 at 07:41:59PM +0100, Michael Riesch wrote: > >> On 11/7/25 18:32, Sakari Ailus wrote: > >>> On Fri, Oct 24, 2025 at 02:51:29PM +0200, Michael Riesch via B4 Relay wrote: > >>>> Habidere, > >>>> > >>>> This series introduces support for the Rockchip Camera Interface (CIF), > >>>> which is featured in many Rockchip SoCs in different variations. > >>>> For example, the PX30 Video Input Processor (VIP) is able to receive > >>>> video data via the Digital Video Port (DVP, a parallel data interface) > >>>> and transfer it into system memory using a double-buffering mechanism > >>>> called ping-pong mode. > >>>> The RK3568 Video Capture (VICAP) unit, on the other hand, features a > >>>> DVP and a MIPI CSI-2 receiver that can receive video data independently > >>>> (both using the ping-pong scheme). > >>>> The different variants may have additional features, such as scaling > >>>> and/or cropping. > >>>> Finally, the RK3588 VICAP unit constitutes an essential piece of the > >>>> camera interface with one DVP, six MIPI CSI-2 receivers, scale/crop > >>>> units, and a data path multiplexer (to scaler units, to ISP, ...). > >>> > >>> I understand both RK3568 and RK3588 include an ISP. Do you have insight on > >>> how would this work, should the support for the ISP be added later on? > >> > >> Short answer: Yes and yes. > >> > >> Long answer: > >> > >> The patch series at hand adds support for the PX30 VIP and the RK3568 > >> VICAP. I cannot really say something about the PX30, but on the RK3568 > >> VICAP and ISP are orthogonal (the ISP features its own MIPI CSI-2 > >> receiver, different from that introduced in this series). Thus, ISP > >> support can be introduced anytime (whenever someone is motivated ;-)). > > > > Won't they both be connected to the same sensor though, and probably the > > same D-PHY in the SoC ? They don't seem entirely separate to me. > > The MIPI CSI-2 DPHY is shared, indeed. Thus, they *maybe technically > could be* connected to the same sensor, but I don't know whether that > works and fail to see why anyone would to such a thing (if it is about > raw capture, the MIPI CSI-2 receiver in the ISP can do that on its own). > > The DPHY can be operated in split mode, with two lanes for VICAP and two > lanes for ISP. This is not implemented yet, but can be done at a later > stage on PHY level (not media related). In this case, ISP and VICAP can > receive data from different subdevices via CSI-2. The two would be part of the same media graph in that case and as there are two CSI-2 receivers and a single PHY, the PHY would probably need to have a sub-device as well, to allow link configuration to be used to select where the PHY is connected. I don't think we have such a setup elsewhere, and supporting this would require changes in the MC framework. How does the media graph look like for the device at the moment? > > BTW the ISP is able to process the data captured by VICAP, but > apparently this includes a RAM round trip (VICAP captures to memory, ISP > operates in mem2mem mode). > > > A block diagram that shows connections between the CSI-2 pins, D-PHY, > > CSI-2 receivers, VICAP and ISP could help. > > > >> Once this patch series is merged, I'll push out changes that introduce > >> support for the RK3588 VICAP. We can discuss the integration of any > >> RK3588 ISP in this scope then -- and there may be some things to discuss > >> as there the VICAP and the ISP(s) are directly connected by means of a > >> MUX unit in the VICAP. > >> > >> Alright? > > -- Kind regards, Sakari Ailus