From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C3D073090E2 for ; Fri, 14 Nov 2025 09:55:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763114121; cv=none; b=O4OKLPzmpXhjO0b6/ryjPoutirPL8AahaQqMnRKVfJDV1JHy4HCz7ygN3MNmWg2NMvjKTqfcTr1DnjDQTeFOeJqlCoNrnrroJ6KxU5WysNpjs2Sx9SGr+iDP1UgAxJlgQfekTVEIn2FC0u/RCQE9y71bb7Hf4uiVGtaLvb/pkOU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763114121; c=relaxed/simple; bh=9voqBgTvR0EvijVtrYph4uWoSfbOx66xvrO82Qt5Ezo=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=cf0HETXS2wELBVYZIWVTlYoC+TNQw8h3wMtCW0eP81rbACnZowQoHUtJhGiiNylKz5LveYAAnPNWR04gm1WLSEdVVCBUfc5L6VC18F7IePv0vKj0aFtCOj1thP0Aq0koCL2H0n8868rTIymBU7OGZ1XpE/Dp6iTU8XPZCd2iluE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 196D51063; Fri, 14 Nov 2025 01:55:06 -0800 (PST) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7DFE53F5A1; Fri, 14 Nov 2025 01:55:12 -0800 (PST) Date: Fri, 14 Nov 2025 09:55:07 +0000 From: Mark Rutland To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Ryan Roberts , Ard Biesheuvel , linux-kernel@vger.kernel.org Subject: Re: [PATCH 0/6] arm64/mm: TTBRx_EL1 related changes Message-ID: References: <20251103052618.586763-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Thu, Nov 13, 2025 at 02:48:44PM +0530, Anshuman Khandual wrote: > On 03/11/25 10:56 AM, Anshuman Khandual wrote: > > This series contains some TTBRx_EL1 related changes, aimed at standardizing > > TTBRx_EL1 register field accesses via tools sysreg format and also explains > > 52 PA specific handling methods via a new macro along with in code comments > > > > This series applies on v6.18-rc4 > > > > Cc: Catalin Marinas > > Cc: Will Deacon > > Cc: Ryan Roberts > > Cc: Ard Biesheuvel > > Cc: linux-arm-kernel@lists.infradead.org > > Cc: linux-kernel@vger.kernel.org > > > > Anshuman Khandual (6): > > arm64/mm: Directly use TTBRx_EL1_ASID_MASK > > arm64/mm: Directly use TTBRx_EL1_CnP > > arm64/mm: Represent TTBR_BADDR_MASK_52 with TTBRx_EL1_BADDR_MASK > > arm64/mm: Ensure correct 48 bit PA gets into TTBRx_EL1 > > arm64/mm: Describe 52 PA folding into TTBRx_EL1 > > arm64/mm: Describe TTBR1_BADDR_4852_OFFSET > > > > arch/arm64/include/asm/asm-uaccess.h | 2 +- > > arch/arm64/include/asm/assembler.h | 3 ++- > > arch/arm64/include/asm/mmu_context.h | 2 +- > > arch/arm64/include/asm/pgtable-hwdef.h | 23 ++++++++++++++++++++--- > > arch/arm64/include/asm/pgtable.h | 5 +++-- > > arch/arm64/include/asm/uaccess.h | 6 +++--- > > arch/arm64/kernel/entry.S | 2 +- > > arch/arm64/kernel/mte.c | 4 ++-- > > arch/arm64/mm/context.c | 8 ++++---- > > arch/arm64/mm/mmu.c | 2 +- > > 10 files changed, 38 insertions(+), 19 deletions(-) > > Gentle ping. Beside [PATCH 4/6] (which can be dropped as indicated by Mark) > any concerns regarding reset of these changes here ? Overall I don;t think this series actually improves anything; it just shuffles things around, and leaves conversions half-done. I don't think we must take this as-is. For patches 1 and 2, the changes would be fine if we were also getting rid of TTBR_ASID_MASK and TTBR_CNP_BIT, but we don't, apparently because those are still used by KVM. It feels like those two patches should be split into a separate series that *only* moves code over to generate sysreg definitions, also updates KVM, and removes the unused legacy definitions. For patch 3, I think the change makes the code harder to read, and harder to understand, because there's no context to explain why we're masking out a single bit. I don't think this is actually an improvement. See below for related notes for patch 5. For patch 4, as above, I think the patch can be dropped. For patch 5, this could be OK, but we should define TTBR_BADDR_52_PA_PIVOT as (51 - 5) and avoid the magic number entirely. IMO it'd be nicer to just extract and re-insert the bits; I think our current logic is unnecessarily micro-optimized so that this can be implemented with a shifted-OR + AND, whereas I think we could burn a temporary register and use BFX + BFI + AND, and that would be clearer as to *which* bits we're trying to move. For patch 6, I guess this is fine; I don't have a strong feeling either way. Mark.