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[34.140.140.54]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47a816938d4sm15340565e9.1.2025.12.09.07.41.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Dec 2025 07:41:10 -0800 (PST) Date: Tue, 9 Dec 2025 15:41:06 +0000 From: Mostafa Saleh To: Robin Murphy Cc: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, will@kernel.org, joro@8bytes.org, Tomasz Nowicki Subject: Re: [PATCH] iommu/io-pgtable-arm: Add misisng concatenated PGD cases Message-ID: References: <20251130194506.593700-1-smostafa@google.com> <18a39079-2285-47fb-b306-040f2bc1bbaa@arm.com> <498bbad4-ea64-4a24-a63f-e131d271990a@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <498bbad4-ea64-4a24-a63f-e131d271990a@arm.com> On Tue, Dec 09, 2025 at 01:33:36PM +0000, Robin Murphy wrote: > On 2025-12-09 12:37 pm, Mostafa Saleh wrote: > > On Tue, Dec 09, 2025 at 11:34:34AM +0000, Robin Murphy wrote: > > > On 2025-11-30 7:45 pm, Mostafa Saleh wrote: > > > > arm_lpae_concat_mandatory() assumes that OAS >= IAS which is not > > > > correct for SMMUs supporting AArch32, and have OAS = 32/36 bits, > > > > as IAS would be 40 bits. > > > > > > But that is only when *using* AArch32 format. The bit in chapter 3.4 of the > > > SMMU architecture is talking about the maximum IAS that an SMMU > > > implementation needs to be able to accommodate based on its configuration, > > > but it does then attempt to clarify that the actual IPA size in use by any > > > given context should depend on the VMSA format in use: > > > > > > "VMSAv8-32 LPAE always supports an IPA size of 40 bits, whereas VMSAv8-64 > > > and VMSAv9-128 limits the maximum IPA size to the maximum PA size." > > > > > > Rule R_SRKBC in the Arm ARM lays out the exact T0SZ constraints with this > > > AArch32/AArch64 detail. > > > > I see, thanks a lot for the explanation, I got confused by the this > > statement: > > Note: If AArch32 is implemented, IAS == MAX(40, OAS), otherwise IAS == OAS. > > Indeed, that appears confusingly contradictory; I've filed a bug. > > > However, I think this is still a bug but somewere else, as at the moment > > the SMMUv3 dirver will use the SMMU IAS (40-bits) as input for AArch64 > > stage-2 page tables, so we need either to limit the IAS as: > > > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > index d16d35c78c06..d21153156daa 100644 > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > @@ -2561,7 +2561,7 @@ static int arm_smmu_domain_finalise(struct arm_smmu_domain *smmu_domain, > > case ARM_SMMU_DOMAIN_S2: > > if (enable_dirty) > > return -EOPNOTSUPP; > > - pgtbl_cfg.ias = smmu->ias; > > + pgtbl_cfg.ias = min(smmu->ias, smmu->oas); > > pgtbl_cfg.oas = smmu->oas; > > fmt = ARM_64_LPAE_S2; > > finalise_stage_fn = arm_smmu_domain_finalise_s2; > > > > Or, don't populate IAS depending on AArch32 support as the driver > > doesn't support it, effectively reverting: > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f0c453dbcce7767cd868deb809ba68083c93954e > > It does appear we've missed the detail here. TBH I'm not really sure why > we're bothering to consider the theoretical maximum IAS at all when it only > makes any difference to a format we've never cared about supporting anyway. > Frankly I'd be inclined to just remove smmu->ias altogether - even if we did > ever want to support LPAE format, it would be just as trivial for that to > hard-code pgtbl_cfg.ias = 40 based on the architecture rules. > Makes sense, I will prepare a patch. Thanks, Mostafa > Thanks, > Robin.