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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-88c5e16668dsm11844456d6.23.2025.12.17.23.03.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Dec 2025 23:04:03 -0800 (PST) Date: Thu, 18 Dec 2025 15:03:56 +0800 From: yuanjiey To: Konrad Dybcio Cc: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com Subject: Re: [PATCH] arm64: dts: qcom: talos: Add PMU support Message-ID: References: <20251217092057.462-1-yuanjie.yang@oss.qualcomm.com> <5d258204-097b-49e1-a53a-d35f846ecfa8@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5d258204-097b-49e1-a53a-d35f846ecfa8@oss.qualcomm.com> X-Proofpoint-GUID: SBfDIKVqPDKysfXBfzZHn61BVu9-9hq1 X-Authority-Analysis: v=2.4 cv=Z8Th3XRA c=1 sm=1 tr=0 ts=6943a765 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=kj9zAlcOel0A:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=l6bYHGOvgJwPg63tIUIA:9 a=CjuIK1q_8ugA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-ORIG-GUID: SBfDIKVqPDKysfXBfzZHn61BVu9-9hq1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE4MDA1NiBTYWx0ZWRfXyQVYzawCeUE2 jcfcXsK0Bs7XbFDGMTskbl2jMk4eyddF9c9MXY+kr3uZN3ca60zisGAfzi16vuejU4pO+wg8shR OA25d4sXBeFveWKM1UY9AHYXzic6UGGAVXZhB5fZtky6mqlIifb9SiqQzxKly/v4WZApbGgBRA3 zuGSqlpmmfEimFaNSWsr/A6TcR9X85xMCmllHY/e3+sIT6LmuOUY7gPbBbQlYhBefbuXBNc50tL We/MDYtZss5guVUXvroL6ys5s6HKQuAhMUA47uocSl8qBlbT1U4NyaIQHbHuX9b3X3QmEFZuyb7 jegCymqJ30SAzXtYsGyTUFg2s5Af/SUmAkXxcFS24IIV+9LjfJ1V3UyBRmmegzm9ey80VORD7Ym kFa/2LbAOH85xoJEhZgtxeyk7wX6fw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-18_01,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 bulkscore=0 malwarescore=0 suspectscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512180056 On Wed, Dec 17, 2025 at 11:07:17AM +0100, Konrad Dybcio wrote: > On 12/17/25 10:20 AM, yuanjie yang wrote: > > From: Yuanjie Yang > > > > Add the PMU node for talos platforms. > > > > Signed-off-by: Yuanjie Yang > > --- > > Check out: > > 9ce52e908bd5 ("arm64: dts: qcom: sm8650: switch to interrupt-cells 4 to add PPI partitions") > 2c06e0797c32 ("arm64: dts: qcom: sm8650: add PPI interrupt partitions for the ARM PMUs") > > You'll have to do the same since the interrupt is shared Get it, will add interrupt-cells 4 add PPI partitions in next patch. Thanks, Yuanjie > Konrad > > > arch/arm64/boot/dts/qcom/talos.dtsi | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi > > index 95d26e313622..3ba1e3c1d1d7 100644 > > --- a/arch/arm64/boot/dts/qcom/talos.dtsi > > +++ b/arch/arm64/boot/dts/qcom/talos.dtsi > > @@ -555,6 +555,16 @@ opp-128000000 { > > }; > > }; > > > > + pmu-a55 { > > + compatible = "arm,cortex-a55-pmu"; > > + interrupts = ; > > + }; > > + > > + pmu-a76 { > > + compatible = "arm,cortex-a76-pmu"; > > + interrupts = ; > > + }; > > + > > psci { > > compatible = "arm,psci-1.0"; > > method = "smc";