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Sun, 21 Dec 2025 05:11:41 -0800 (PST) Received: from mitya-t14-2025 ([2a02:a31b:20c3:6680:4cc9:1698:dce5:4976]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b803d3cea32sm695782866b.34.2025.12.21.05.11.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Dec 2025 05:11:41 -0800 (PST) Date: Sun, 21 Dec 2025 14:11:34 +0100 From: Dmytro Maluka To: Baolu Lu Cc: David Woodhouse , iommu@lists.linux.dev, Joerg Roedel , Will Deacon , Robin Murphy , linux-kernel@vger.kernel.org, "Vineeth Pillai (Google)" , Aashish Sharma , Grzegorz Jaszczyk , Chuanxiao Dong , Kevin Tian Subject: Re: [PATCH 1/2] iommu/vt-d: Ensure memory ordering in context entry updates Message-ID: References: <20251221014302.17738-1-dmaluka@chromium.org> <20251221014302.17738-2-dmaluka@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Sun, Dec 21, 2025 at 05:04:27PM +0800, Baolu Lu wrote: > On 12/21/25 09:43, Dmytro Maluka wrote: > > +static inline void context_set_bits(u64 *ptr, u64 mask, u64 bits) > > +{ > > + u64 old; > > + > > + old = READ_ONCE(*ptr); > > + WRITE_ONCE(*ptr, (old & ~mask) | bits); > > +} > > Add a line to ensures that the input "bits" cannot overflow the assigned > "mask". > > static inline void context_set_bits(u64 *ptr, u64 mask, u64 bits) > { > u64 val; > > val = READ_ONCE(*ptr); > val &= ~mask; > val |= (bits & mask); > WRITE_ONCE(*ptr, val); > } Makes sense. And then worth doing the same in pasid_set_bits() as well? Actually we can use the same helper for both context and pasid entries (rename it e.g. to entry_set_bits()). > > static inline void context_set_present(struct context_entry *context) > > { > > - context->lo |= 1; > > + context_set_bits(&context->lo, 1 << 0, 1); > > } > > How about adding a smp_wmb() before setting the present bit? Maybe it's > unnecessary for x86 architecture, but at least it's harmless and more > readable. Or not? > > static inline void context_set_present(struct context_entry *context) > { > smp_wmb(); > context_set_bits(&context->lo, 1ULL << 0, 1ULL); > } Maybe... And if so, then in pasid_set_present() as well? Actually this would make a slight behavioral difference even on x86: right now this patch only provides ordering of context entry updates between each other, while smp_wmb() would add a full compiler barrier here. So this barrier may be redundant as long as we always use these context_*() helpers (and thus always use WRITE_ONCE) for any updates of context entries. On the other hand, it might make it more robust if we still occasionally do that without WRITE_ONCE, for example in context_entry_set_pasid_table() which I also changed to use WRITE_ONCE in this patch.