From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 31951221290 for ; Mon, 5 Jan 2026 05:35:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767591320; cv=none; b=QMKerwmhQvsLWqS7ahBZYccKnAwLDFM/nou0klca+dxk3yxWuzyywWIsUAmmbBbO6cop14n1oceLSEGob5MccQkCuUnlenPzGk1iCaXbf59hmbyZ6v/8Orw8pD7qk62y6MCf2CaNOjw/UO6ZoKiiqEHDYEAdq6LS6IzAmnbqUuA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767591320; c=relaxed/simple; bh=4pUPYK+4Utxj/IiIhtJaI6FRtEKKO2qPvGMbN4EyGWA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=K9rKTCXtAYpJFcBHqZ+T6swhc/ud0nvQszSssflntx0cQnfu//trb/vDD4E5eE+rOY7WfrqFUIHORWTBNCAWNdFLrL5SN6EprMPvCAiydWGdw5DUE4+L6YwmNWChmzH10TnmfxZ8mioiqeZSKJYqrxHc3ljjpS1tbHcmEhy9TbQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C444D339; Sun, 4 Jan 2026 21:35:11 -0800 (PST) Received: from localhost (a079125.arm.com [10.164.21.37]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CDD353F694; Sun, 4 Jan 2026 21:35:17 -0800 (PST) Date: Mon, 5 Jan 2026 11:05:14 +0530 From: Linu Cherian To: Ryan Roberts Cc: Will Deacon , Ard Biesheuvel , Catalin Marinas , Mark Rutland , Linus Torvalds , Oliver Upton , Marc Zyngier , Dev Jain , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 04/13] arm64: mm: Push __TLBI_VADDR() into __tlbi_level() Message-ID: References: <20251216144601.2106412-1-ryan.roberts@arm.com> <20251216144601.2106412-5-ryan.roberts@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251216144601.2106412-5-ryan.roberts@arm.com> On Tue, Dec 16, 2025 at 02:45:49PM +0000, Ryan Roberts wrote: > From: Will Deacon > > The __TLBI_VADDR() macro takes an ASID and an address and converts them > into a single argument formatted correctly for a TLB invalidation > instruction. > > Rather than have callers worry about this (especially in the case where > the ASID is zero), push the macro down into __tlbi_level() via a new > __tlbi_level_asid() helper. > > Signed-off-by: Will Deacon > Signed-off-by: Ryan Roberts > --- > arch/arm64/include/asm/tlbflush.h | 14 ++++++++++---- > arch/arm64/kernel/sys_compat.c | 2 +- > arch/arm64/kvm/hyp/nvhe/mm.c | 2 +- > arch/arm64/kvm/hyp/pgtable.c | 4 ++-- > 4 files changed, 14 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index 31f43d953ce2..39717f98c31e 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -150,9 +150,10 @@ static __always_inline void ipas2e1is(u64 arg) > __tlbi(ipas2e1is, arg); > } > > -static __always_inline void __tlbi_level(tlbi_op op, u64 addr, u32 level) > +static __always_inline void __tlbi_level_asid(tlbi_op op, u64 addr, u32 level, > + u16 asid) > { > - u64 arg = addr; > + u64 arg = __TLBI_VADDR(addr, asid); > > if (alternative_has_cap_unlikely(ARM64_HAS_ARMv8_4_TTL) && level <= 3) { > u64 ttl = level | (get_trans_granule() << 2); > @@ -164,6 +165,11 @@ static __always_inline void __tlbi_level(tlbi_op op, u64 addr, u32 level) > op(arg); > } > > +static inline void __tlbi_level(tlbi_op op, u64 addr, u32 level) > +{ > + __tlbi_level_asid(op, addr, level, 0); > +} > + > /* > * This macro creates a properly formatted VA operand for the TLB RANGE. The > * value bit assignments are: > @@ -501,8 +507,7 @@ do { \ > if (!system_supports_tlb_range() || \ > __flush_pages == 1 || \ > (lpa2 && __flush_start != ALIGN(__flush_start, SZ_64K))) { \ > - addr = __TLBI_VADDR(__flush_start, asid); \ > - __tlbi_level(op, addr, tlb_level); \ > + __tlbi_level_asid(op, __flush_start, tlb_level, asid); \ > __flush_start += stride; \ > __flush_pages -= stride >> PAGE_SHIFT; \ > continue; \ > @@ -675,5 +680,6 @@ static inline bool huge_pmd_needs_flush(pmd_t oldpmd, pmd_t newpmd) > #define huge_pmd_needs_flush huge_pmd_needs_flush > > #undef __tlbi_user > +#undef __TLBI_VADDR > #endif > #endif > diff --git a/arch/arm64/kernel/sys_compat.c b/arch/arm64/kernel/sys_compat.c > index 4a609e9b65de..ad4857df4830 100644 > --- a/arch/arm64/kernel/sys_compat.c > +++ b/arch/arm64/kernel/sys_compat.c > @@ -36,7 +36,7 @@ __do_compat_cache_op(unsigned long start, unsigned long end) > * The workaround requires an inner-shareable tlbi. > * We pick the reserved-ASID to minimise the impact. > */ > - __tlbi(aside1is, __TLBI_VADDR(0, 0)); > + __tlbi(aside1is, 0UL); > dsb(ish); > } > > diff --git a/arch/arm64/kvm/hyp/nvhe/mm.c b/arch/arm64/kvm/hyp/nvhe/mm.c > index ae8391baebc3..581385b21826 100644 > --- a/arch/arm64/kvm/hyp/nvhe/mm.c > +++ b/arch/arm64/kvm/hyp/nvhe/mm.c > @@ -270,7 +270,7 @@ static void fixmap_clear_slot(struct hyp_fixmap_slot *slot) > * https://lore.kernel.org/kvm/20221017115209.2099-1-will@kernel.org/T/#mf10dfbaf1eaef9274c581b81c53758918c1d0f03 > */ > dsb(ishst); > - __tlbi_level(vale2is, __TLBI_VADDR(addr, 0), level); > + __tlbi_level(vale2is, addr, level); > dsb(ish); > isb(); > } > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > index 947ac1a951a5..9292c569afe6 100644 > --- a/arch/arm64/kvm/hyp/pgtable.c > +++ b/arch/arm64/kvm/hyp/pgtable.c > @@ -472,14 +472,14 @@ static int hyp_unmap_walker(const struct kvm_pgtable_visit_ctx *ctx, > > kvm_clear_pte(ctx->ptep); > dsb(ishst); > - __tlbi_level(vae2is, __TLBI_VADDR(ctx->addr, 0), TLBI_TTL_UNKNOWN); > + __tlbi_level(vae2is, ctx->addr, TLBI_TTL_UNKNOWN); > } else { > if (ctx->end - ctx->addr < granule) > return -EINVAL; > > kvm_clear_pte(ctx->ptep); > dsb(ishst); > - __tlbi_level(vale2is, __TLBI_VADDR(ctx->addr, 0), ctx->level); > + __tlbi_level(vale2is, ctx->addr, ctx->level); > *unmapped += granule; > } > > -- > 2.43.0 > Reviewed-by: Linu Cherian