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Mon, 19 Jan 2026 05:56:35 +0000 Date: Mon, 19 Jan 2026 13:53:47 +0800 From: Yan Zhao To: "Edgecombe, Rick P" CC: "seanjc@google.com" , "Du, Fan" , "Li, Xiaoyao" , "Huang, Kai" , "kvm@vger.kernel.org" , "Hansen, Dave" , "thomas.lendacky@amd.com" , "vbabka@suse.cz" , "tabba@google.com" , "david@kernel.org" , "kas@kernel.org" , "linux-kernel@vger.kernel.org" , "Weiny, Ira" , "francescolavra.fl@gmail.com" , "pbonzini@redhat.com" , "ackerleytng@google.com" , "nik.borisov@suse.com" , "binbin.wu@linux.intel.com" , "Yamahata, Isaku" , "Peng, Chao P" , "michael.roth@amd.com" , "Annapurve, Vishal" , "sagis@google.com" , "Gao, Chao" , "Miao, Jun" , "jgross@suse.com" , "pgonda@google.com" , "x86@kernel.org" Subject: Re: [PATCH v3 00/24] KVM: TDX huge page support for private memory Message-ID: Reply-To: Yan Zhao References: <6184812b4449947395417b07ae3bad2f191d178f.camel@intel.com> Content-Type: text/plain; charset="iso-8859-1" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <6184812b4449947395417b07ae3bad2f191d178f.camel@intel.com> X-ClientProxiedBy: KU2P306CA0085.MYSP306.PROD.OUTLOOK.COM (2603:1096:d10:3a::15) To DS7PR11MB5966.namprd11.prod.outlook.com (2603:10b6:8:71::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS7PR11MB5966:EE_|DS4PPF75D68BA1B:EE_ X-MS-Office365-Filtering-Correlation-Id: 8552978e-c350-4650-230e-08de571f80ef X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?iso-8859-1?Q?XX0hxx6xRhubJ5Nb5BPtMr6QG4bp63ZmMbwdWl8LrwJ11/FtrQFnQjHNlu?= =?iso-8859-1?Q?yVCPAFNAL51dpJgjCMnPag+GQ43JG3FH0v2+Xoi1orL4is4MHxEhtIzYxg?= =?iso-8859-1?Q?FUrRFIMVHbCpqCVROxaacNYtvJiL/xt+fIKz9yYIQKW00Aq42YQdANUZO/?= =?iso-8859-1?Q?jnCkj4kWC+K6K8pIvMp2oUk5CkSQWmeeS4VBQGDoHeTtM0s3cTw8NTZ5eC?= =?iso-8859-1?Q?bPLmOlapwHySkKDI8b6EpIwZoJ6REEW/OMmYvdthXOmfrYqZP5R31eby+H?= =?iso-8859-1?Q?CagKgnOTIUgknXJ40gIynFWcW5JhitAB0Grolkv0j2B68qPwAZmXJkBY1F?= =?iso-8859-1?Q?zz4ZOie4X6vtkdfPBoUwWY7jIh4Sk7GhjwuZSBiuiUf7d5dM6ihWiKD7MC?= =?iso-8859-1?Q?dSEhbg6b9/dRw+bGxXX1Dcnlaew2l9etEMvGUcweWlisR6kd03cI9dRODO?= =?iso-8859-1?Q?MdHfsE5MLl86mzbtkE19qXwaZSSmNSnOrmFiT3DKNV9E23CoZYo04+wvJi?= =?iso-8859-1?Q?Z42NnJEltYlGVTurvWuQ8jtR0w3WcIRmUYsLug4XOVu++VqMVBFd0EmsEK?= =?iso-8859-1?Q?4MgPAA1nDiZjkwpShCSwk32WgfnsSecfzEPxNiNyvrXJRyBcyFhTtKJn0M?= =?iso-8859-1?Q?dhAjtRSM2SPdsHJPzCn09HgA7A2CPf+RHVXjoeRofHLBTHygn8E1v0aE1F?= =?iso-8859-1?Q?a/WFUYvGyHp9NviVQmKRwcNvxyBNpFJ6VJ5c5AB7UKwOVvgxcpNW99yuO6?= =?iso-8859-1?Q?oNSziXHi9Cw+IcjdOuGS5Hs5XlGwAuy1iuPgUadzZEDfecs0XvAqnk4Lxi?= =?iso-8859-1?Q?GZ8+Pu8H2aan54VRIG/gYoC5fD4cparmgL+GjfXru+wKb+UIUebFZOzFQO?= =?iso-8859-1?Q?ujhhLOy4a8MJBpy1BUzubZChMXj7z6Uq07M3AtYqPmDKWAWLZCDs2lTDrC?= =?iso-8859-1?Q?2KabV7Whq5Wx2cwIZ6ey8zNIzGvh6jJtQXiLLFgtfDvqxebofbjs0pLYA2?= =?iso-8859-1?Q?x4tINOYUpWDuKwPurQ9pq5yWSa7Mpv/fUcvJoLVMfV2Dr9TmXQNLNiSYmN?= =?iso-8859-1?Q?S/9+eWH0UV+v0CUZXW6T/fybLUnQ1kHB8rlqaJ5W/H3oSITR9aX7KMaYO0?= =?iso-8859-1?Q?3ch+6H44APuFOxXUSJJN2doVNW9oinfneJtBJl98eIIh4duCXBwfuBWvZY?= =?iso-8859-1?Q?NXebOntRG1L47JKiIBLqk4gxfjrHRx9x1vA02E8Nb14Q4NIS9Jpm0Rji3u?= =?iso-8859-1?Q?p29uAcdEU+8f4J0ICsv4uMkyW2ejT+Ah1/qBa0HJT6XN+ivnsgdF0rM6xy?= =?iso-8859-1?Q?BiR4m1OfiU4M7aFzo71/dXTIb+lJpa0kauT3g+4OC+9K5/yI1cn+vIs9Is?= =?iso-8859-1?Q?86+DDlYtY6mF973eurYsHCv5WEYuWnqO5dCg3R0Z4nRYuIVd6yMVslPULw?= =?iso-8859-1?Q?VsITjs09DAR55hNGpLBicknAgW8QBAzmuQk9FwikRaRYQwzQG6Nvnnp+0k?= =?iso-8859-1?Q?5oKebchHakytrk0oH003nGOYTbfRQctsst2vidxcUaGpbMtBbWrYI5ADAx?= =?iso-8859-1?Q?Abn2ZMVA+N+2c3cmzb8Z6ydddiq6ZtSri8q9AANOh3I3bjE6XYyL2CLuLp?= =?iso-8859-1?Q?J3aBeFcEDQZPW3wPGSLCntfyym/kg5tMjceggtubDKYLdf1CYx+DUu9Xph?= =?iso-8859-1?Q?DeyrbTiODgRp/2wnB4rn3As9RaClL2tm1jn9E5rhj/mmebm5wZIIoQTvd/?= =?iso-8859-1?Q?f3X7YMdf2EAESSocdczMnUmnPVKrInHTU/ejKV74mlFSgS5wNCs6Eyl4Ja?= =?iso-8859-1?Q?ZZB3TbhNvw=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 8552978e-c350-4650-230e-08de571f80ef X-MS-Exchange-CrossTenant-AuthSource: DS7PR11MB5966.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2026 05:56:35.3664 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ti9aPIDpyyPmXnS/dfQvYzJ4dQ8WHkgq5uS6xOHa7s85o4IVv5G9HRSLM82++mMCGz20SDEAPEcEaCKWIXKofA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PPF75D68BA1B X-OriginatorOrg: intel.com On Sat, Jan 17, 2026 at 12:58:02AM +0800, Edgecombe, Rick P wrote: > On Fri, 2026-01-16 at 08:31 -0800, Sean Christopherson wrote: > > > Dave wants safety for the TDX pages getting handed to the module. > > > > Define "safety".  As I stressed earlier, blinding retrieving a > > "struct page" and dereferencing that pointer is the exact opposite of > > safe. > > I think we had two problems. > > 1. Passing in raw PA's via u64 led to buggy code. IIRC we had a bug > with this that was caught before it went upstream. So a page needs a > real type of some sort. > > 2. Work was done on the tip side to prevent non-TDX capable memory from > entering the page allocator. With that in place, by requiring struct > page, TDX code can know that it is getting the type of memory it worked > hard to guarantee was good. > > You are saying that shifting a PFN to a struct page blindly doesn't > actually guarantee that it meets those requirements. Makes sense. > > For (1) we can just use any old type I think - pfn_t, etc. As we > discussed in the base series. > > For (2) we need to check that the memory came from the page allocator, > or otherwise is valid TDX memory somehow. That is at least the only > check that makes sense to me. > > There was some discussion about refcounts somewhere in this thread. I > don't think it's arch/x86's worry. Then Yan was saying something last > night that I didn't quite follow. We said, let's just resume the > discussion on the list. So she might suggest another check. Hmm, I previously had a concern about passing "struct page *" as the SEAMCALL wrapper parameter. For example, when we do sanity checks for valid TDX memory in tdh_mem_page_aug(), we need to do the sanity check on every page, right? However, with base_page + npages, it's not easy to get the ith page's pointer without first ensuring the pages are contained in a single folio. It would also be superfluous if we first get base_pfn from base_page, and then derive the ith page from base_pfn + i. IIUC, this concern should be gone as Dave has agreed to use "pfn" as the SEAMCALL parameter [1]? Then should we invoke "KVM_MMU_WARN_ON(!tdx_is_convertible_pfn(pfn));" in KVM for every pfn of a huge mapping? Or should we keep the sanity check inside the SEAMCALL wrappers? BTW, I have another question about the SEAMCALL wrapper implementation, as Kai also pointed out in [2]: since the SEAMCALL wrappers now serve as APIs available to callers besides KVM, should the SEAMCALL wrappers return TDX_OPERAND_INVALID or WARN_ON() (or WARN_ON_ONCE()) on sanity check failure? By returning TDX_OPERAND_INVALID, the caller can check the return code, adjust the input or trigger WARN_ON() by itself; By triggering WARN_ON() directly in the SEAMCALL wrapper, we need to document this requirement for the SEAMCALL wrappers and have the caller invoke the API correctly. So, it looks that "WARN_ON() directly in the SEAMCALL wrapper" is the preferred approach, right? [1] https://lore.kernel.org/all/d119c824-4770-41d2-a926-4ab5268ea3a6@intel.com/ [2] https://lore.kernel.org/all/baf6df2cc63d8e897455168c1bf07180fc9c1db8.camel@intel.com