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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-890770cc7b1sm127049726d6.5.2026.01.11.19.31.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jan 2026 19:31:07 -0800 (PST) Date: Mon, 12 Jan 2026 11:30:59 +0800 From: yuanjiey To: Konrad Dybcio Cc: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, krzysztof.kozlowski@linaro.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com Subject: Re: [PATCH 1/2] drm/msm/dpu: fix mismatch between power and frequency Message-ID: References: <20260109083808.1047-1-yuanjie.yang@oss.qualcomm.com> <20260109083808.1047-2-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-ORIG-GUID: BMg4LM_vb38fUtrTxKTSaDjTVI_VPhg4 X-Authority-Analysis: v=2.4 cv=GNMF0+NK c=1 sm=1 tr=0 ts=69646afd cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=kj9zAlcOel0A:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=BS6H7PxNumziHjRwYM4A:9 a=CjuIK1q_8ugA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-GUID: BMg4LM_vb38fUtrTxKTSaDjTVI_VPhg4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEyMDAyNyBTYWx0ZWRfX8EcDqztbxVAz WeSo/TZcaJkV3FaH65PHMx5G+vyTrQ8J39CXtrv42d34LkSaEiMbTp7uygupRR3fdzbX4dcSMmQ IYUNqqGu3Y+K5t9YLVLhhIlhOiaf1OZdRaT3cPxdVM92WJV1UkwWqAksJ3CN6pzDucLoL79qUVy WtkOyZ/qFuyazafuf3IKKxAmUss2ad9Gae1UpfEwz45ZhbfohvjKDsRc6Qii2OyhUtDCTxBPD5N UdeiqzMr12kP0dLKxI8I542bvjJ+BuW4dK+VWfqfOyPOnMurMm3gGN+LSf9mTjbQJPqECkQvfv+ 7M0enGQReQXGPjoDzIUVT5CzzNsqypIR1ACaHoagmaRQSYfzkZqPhXr6MzvHhG0wUvgg/eSSnKg 6EWAKx3RbfxwSZxRCMAcZLJzCQv4WHHrU8hKILOG+F1ak7isKIGmZ0iSmU0heNefwBS8Ql+pKjp RMEHXSN1VRWjYFe6uCQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-11_09,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 bulkscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601120027 On Fri, Jan 09, 2026 at 11:44:48AM +0100, Konrad Dybcio wrote: > On 1/9/26 9:38 AM, yuanjie yang wrote: > > From: Yuanjie Yang > > > > During DPU runtime suspend, calling dev_pm_opp_set_rate(dev, 0) drops > > the MMCX rail to MIN_SVS while the core clock frequency remains at its > > original (highest) rate. When runtime resume re-enables the clock, this > > may result in a mismatch between the rail voltage and the clock rate. > > > > For example, in the DPU bind path, the sequence could be: > > cpu0: dev_sync_state -> rpmhpd_sync_state > > cpu1: dpu_kms_hw_init > > timeline 0 ------------------------------------------------> t > > > > After rpmhpd_sync_state, the voltage performance is no longer guaranteed > > to stay at the highest level. During dpu_kms_hw_init, calling > > dev_pm_opp_set_rate(dev, 0) drops the voltage, causing the MMCX rail to > > fall to MIN_SVS while the core clock is still at its maximum frequency. > > When the power is re-enabled, only the clock is enabled, leading to a > > situation where the MMCX rail is at MIN_SVS but the core clock is at its > > highest rate. In this state, the rail cannot sustain the clock rate, > > which may cause instability or system crash. > > So what this message essentially says is that dev_pm_opp_set_rate(dev, 0) > doesn't actually set the rate of "0" (or any other rate, unless opp-level > is at play), nor does it disable the clock. > > Seems like a couple of our drivers make this oversight.. > > I see that originally calling dev_pm_opp_set_rate(dev, 0) was forbidden, > up until Commit cd7ea582866f ("opp: Make dev_pm_opp_set_rate() handle freq > = 0 to drop performance votes").. > > In fact, > > $ rg 'dev_pm_opp_set_rate\(.*, 0\)' > > returns exclusively Qualcomm drivers where I believe the intention is always > to disable the clock.. perhaps we should just do that instead. We don't have > to worry about setting F_MIN beforehand, because a disabled clock won't be > eating up power and when enabling it back up, calling opp_set_rate with a > non-zero frequency will bring back the rails to a suitable level Yes, calling opp_set_rate with a non-zero frequency will bring back the rails to a suitable level. The other steps are unnecessary. And here I just choose the highest freq, because I see dpu binding patch: dpu_kms_init(struct drm_device *ddev) use highest freq to do initialization. I want to keep it consistent with the previous initialization logic. Thanks, Yuanjie > > Konrad