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Tue, 27 Jan 2026 01:31:48 -0800 (PST) X-Received: by 2002:a17:903:1aae:b0:2a8:7814:47ce with SMTP id d9443c01a7336-2a8781449cfmr6915135ad.23.1769506307531; Tue, 27 Jan 2026 01:31:47 -0800 (PST) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a802fdd4e8sm112566615ad.99.2026.01.27.01.31.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jan 2026 01:31:46 -0800 (PST) Date: Tue, 27 Jan 2026 15:01:41 +0530 From: Abhinaba Rakshit To: Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Neeraj Soni , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org Subject: Re: [PATCH v3 0/3] Enable ICE clock scaling Message-ID: References: <20260123-enable-ufs-ice-clock-scaling-v3-0-d0d8532abd98@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI3MDA3NyBTYWx0ZWRfXw46bEmgFKLYO k+pLJ2t5JSQzdiqvyxJo8kV7JZqyLpgaIIjiZ0+Uzuac8p+31/t82Tep0GdqWeDwmxUUloWQDCk 3aqFZ6t8UFOBpbLSlDYyPQdqQ8Px7v9jxSX2bl9szz+dDlvgntn1P2Dxmc3N5cu8AfvM0VY6RPx 0J+vrRbfhzJcPGh47pTXWrCWk6l6AKrj/NKsdA4JxwQXlghrLpuIL+5VWA9RByLh8UHaOTpivIp 3f28F2T1j8S0T+Fl0NT5GyKROvWTbYNtzzHjIZbfsRm+NAVCR/4cNlh3yKPjslwgm1bl1VCwkg1 ZhOGeI9EFlfPY7HQ+9VXFjpo9Z8MOtQl70/0eiWRdMa4FAoqhIfACKckGDlL9icXJ6U03N3PiHQ bg5+qy6fXUHSErO5z2Cy2Abz9A/rSGFSKNsbhrsDFZMqkzAIZsiXjmludMUmgROd2lhOjunu/2+ Ii0yuVdQVmmUjcMZccw== X-Proofpoint-ORIG-GUID: 8VK_5bfoS8IytRZhne_LQY0JZlmVDtlb X-Authority-Analysis: v=2.4 cv=Hvh72kTS c=1 sm=1 tr=0 ts=69788604 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=A3LgJq9kZUdRc3Vt2WcA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: 8VK_5bfoS8IytRZhne_LQY0JZlmVDtlb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-27_01,2026-01-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 suspectscore=0 phishscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601270077 On Fri, Jan 23, 2026 at 09:18:36PM +0200, Dmitry Baryshkov wrote: > On Fri, Jan 23, 2026 at 12:42:11PM +0530, Abhinaba Rakshit wrote: > > Introduce support for dynamic clock scaling of the ICE (Inline Crypto Engine) > > using the OPP framework. During ICE device probe, the driver now attempts to > > parse an optional OPP table from the ICE-specific device tree node to > > determine minimum and maximum supported frequencies for DVFS-aware operations. > > API qcom_ice_scale_clk is exposed by ICE driver and is invoked by UFS host > > controller driver in response to clock scaling requests, ensuring coordination > > between ICE and host controller. > > > > For MMC controllers that do not support clock scaling, the ICE clock frequency > > is kept aligned with the MMC controller’s clock rate (TURBO) to ensure > > consistent operation. > > > > Dynamic clock scaling based on OPP tables enables better power-performance > > trade-offs. By adjusting ICE clock frequencies according to workload and power > > constraints, the system can achieve higher throughput when needed and > > reduce power consumption during idle or low-load conditions. > > > > The OPP table remains optional, absence of the table will not cause > > probe failure. However, in the absence of an OPP table, ICE clocks will > > remain at their default rates, which may limit performance under > > high-load scenarios or prevent performance optimizations during idle periods. > > > > Signed-off-by: Abhinaba Rakshit > > --- > > Changes in v3: > > - Avoid clock scaling in case of legacy bindings as suggested. > > - Use of_device_is_compatible to distinguish between legacy and non-legacy bindings. > > - Link to v2: https://lore.kernel.org/r/20251121-enable-ufs-ice-clock-scaling-v2-0-66cb72998041@oss.qualcomm.com > > > > Changes in v2: > > - Use OPP-table instead of freq-table-hz for clock scaling. > > - Enable clock scaling for legacy targets as well, by fetching frequencies from storage opp-table. > > - Introduce has_opp variable in qcom_ice structure to keep track, if ICE instance has dedicated OPP-table registered. > > - Combined the changes for patch-series <20251001-set-ice-clock-to-turbo-v1-1-7b802cf61dda@oss.qualcomm.com> as suggested. > > - Link to v1: https://lore.kernel.org/r/20251001-enable-ufs-ice-clock-scaling-v1-0-ec956160b696@oss.qualcomm.com > > > > --- > > Abhinaba Rakshit (3): > > DT binding changes should be a part of the same series. Sure, will bring the dt-bindings change to this patchseries.