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Tue, 27 Jan 2026 01:38:06 -0800 (PST) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-353f5f96293sm2017007a91.0.2026.01.27.01.38.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jan 2026 01:38:05 -0800 (PST) Date: Tue, 27 Jan 2026 15:08:00 +0530 From: Abhinaba Rakshit To: Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Neeraj Soni , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org Subject: Re: [PATCH v3 1/3] soc: qcom: ice: Add OPP-based clock scaling support for ICE Message-ID: References: <20260123-enable-ufs-ice-clock-scaling-v3-0-d0d8532abd98@oss.qualcomm.com> <20260123-enable-ufs-ice-clock-scaling-v3-1-d0d8532abd98@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI3MDA3OCBTYWx0ZWRfX6eHMy4AdLKkQ ExDnDGBjvU1fr6j2fp8gsibBqBY49kSyyIW+qgxzSyiVt7OvL1vOZaL5FBk7i/K7kk7/dgeQ+qv y3RpQ9ouLOKsSxqrruk0Dx3IAXeSkzKdK/IVKrXQNZIDoX/kfgAatLGgW58WQHJKzURp9Xi4Lxg 81SwoA+jCnIm2BpYlFYi2g26xkCMKRTm7tsVpUcAGEgpz4HkDP61hWqRTeCMt3HU52g2BvmIybu BBL+W9HCFTtIpDQD+nK76saLIQIv8FQt43clrZmxW26lXi5T/uFIGdbGAT7+yQDe7EvTY9a+Mqh dk5I3oXO4KbF+VO1UmTGysTQotIha7QbDUNGc9J8HXMeG771m/L7YxaSByZ3ZnXwYRGfC93VXAg IQmhpPECkempcLxJfXTejNjuEY0C/4L0StlsuH+XBr6TW6ETlTJV39SAry+wh5zcP6VQLviA93N zojZ292zFHGF1dKwPdQ== X-Authority-Analysis: v=2.4 cv=Qelrf8bv c=1 sm=1 tr=0 ts=6978877f cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=kj9zAlcOel0A:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=J-iJWbdkTBbMhk0S1ZMA:9 a=CjuIK1q_8ugA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: oSbnGxl3Sd1mqoPKOVmJkiAi32i_d6Xp X-Proofpoint-GUID: oSbnGxl3Sd1mqoPKOVmJkiAi32i_d6Xp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-27_01,2026-01-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 adultscore=0 phishscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601270078 On Fri, Jan 23, 2026 at 09:21:40PM +0200, Dmitry Baryshkov wrote: > On Fri, Jan 23, 2026 at 12:42:12PM +0530, Abhinaba Rakshit wrote: > > Register optional operation-points-v2 table for ICE device > > and aquire its minimum and maximum frequency during ICE > > device probe. > > > > Introduce clock scaling API qcom_ice_scale_clk which scale ICE > > core clock if valid (non-zero) frequencies are obtained from > > OPP-table. Disable clock scaling if OPP-table is not registered. > > > > When an ICE-device specific OPP table is available, use the PM OPP > > framework to manage frequency scaling and maintain proper power-domain > > constraints. > > > > Signed-off-by: Abhinaba Rakshit > > --- > > drivers/soc/qcom/ice.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++ > > include/soc/qcom/ice.h | 1 + > > 2 files changed, 64 insertions(+) > > > > diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c > > index b203bc685cadd21d6f96eb1799963a13db4b2b72..ca6a7df7a6827378af1f013c7e62a835d1b80cc5 100644 > > --- a/drivers/soc/qcom/ice.c > > +++ b/drivers/soc/qcom/ice.c > > @@ -16,6 +16,7 @@ > > #include > > #include > > #include > > +#include > > > > #include > > > > @@ -111,6 +112,9 @@ struct qcom_ice { > > bool use_hwkm; > > bool hwkm_init_complete; > > u8 hwkm_version; > > + unsigned long max_freq; > > + unsigned long min_freq; > > + bool has_opp; > > }; > > > > static bool qcom_ice_check_supported(struct qcom_ice *ice) > > @@ -549,10 +553,29 @@ int qcom_ice_import_key(struct qcom_ice *ice, > > } > > EXPORT_SYMBOL_GPL(qcom_ice_import_key); > > > > +int qcom_ice_scale_clk(struct qcom_ice *ice, bool scale_up) > > +{ > > + int ret = 0; > > + > > + if (!ice->has_opp) > > + return ret; > > + > > + if (scale_up && ice->max_freq) > > + ret = dev_pm_opp_set_rate(ice->dev, ice->max_freq); > > + else if (!scale_up && ice->min_freq) > > + ret = dev_pm_opp_set_rate(ice->dev, ice->min_freq); > > Do we expect that there allways will be only two entries in the OPP? > If so, it should be a part of the bindings. If not, please design the > API with more flexibility in mind. No. Thanks for pointing this out. With OPP v2 being used we can indeed, support multiple frequencies. Also UFS core using devfreq clock scaling can scale among multiple-frequencies depending on the load. Will update the patch-set, with multi-frequency scale support.