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Sun, 01 Feb 2026 22:37:48 -0800 (PST) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82379b4e96dsm14489764b3a.23.2026.02.01.22.37.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Feb 2026 22:37:48 -0800 (PST) Date: Mon, 2 Feb 2026 12:07:41 +0530 From: Abhinaba Rakshit To: Krzysztof Kozlowski Cc: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Neeraj Soni , Herbert Xu , "David S. Miller" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v4 1/4] dt-bindings: crypto: ice: add operating-points-v2 property for QCOM ICE Message-ID: References: <20260128-enable-ufs-ice-clock-scaling-v4-0-260141e8fce6@oss.qualcomm.com> <20260128-enable-ufs-ice-clock-scaling-v4-1-260141e8fce6@oss.qualcomm.com> <20260128-amigurumi-viper-of-gallantry-69ab8a@quoll> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260128-amigurumi-viper-of-gallantry-69ab8a@quoll> X-Proofpoint-ORIG-GUID: oRjySBeCUhpiJ8G28Wr5X71lbnDs-8JP X-Authority-Analysis: v=2.4 cv=FNYWBuos c=1 sm=1 tr=0 ts=6980463e cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=kj9zAlcOel0A:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=040W-1HjkB6UkxdISe8A:9 a=CjuIK1q_8ugA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjAyMDA1NSBTYWx0ZWRfX7gxflFo6Ci6O 9ETx9axfpSCCEkT5m05x3Z/Y1WW5g5uJH+Ws/0r00WVrd5YQm2TtVadSgpimVQZuQaHiTR7LkUq ih0B5BpxZ0AajV/PcaXexpBITdJaausqMvyjW135eyGo921WzK6svoPA1sbo4yZi7L4zZE3yfYS 7wkQ/lKynTj87C9PK2Z+YU4W6B0dTH6wwAe8g37nNHPy2FdPjIs2E/fv+wIQyxwQf19BC/H04eu AJtfxsvVAdXFPDO/E3rH9VzTY6XEnkKXgoWyW+Sy5MVlgJo1yR2c7bLP76j8UkgY7Qz722Uhgb8 cc/I9ry9oedwYz3ahYegBASfH/YM23abMr+yCq7HCcRV3PDtA1N4InyDx5PLNTS6ObB0w49ikHY s0+DrMWsfKimiIBF3TjfpzGfsmlaXRJNTlp5NDGgtOHM9W7HmOCNYldzard2tCOx4ytrVCA/yHa JmUZWPb7GxVRkPhXy2g== X-Proofpoint-GUID: oRjySBeCUhpiJ8G28Wr5X71lbnDs-8JP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-02_02,2026-01-30_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 clxscore=1015 spamscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602020055 On Wed, Jan 28, 2026 at 12:00:57PM +0100, Krzysztof Kozlowski wrote: > On Wed, Jan 28, 2026 at 02:16:40PM +0530, Abhinaba Rakshit wrote: > > Add support for specifying OPPs for the Qualcomm Inline Crypto Engine > > by allowing the use of the standard "operating-points-v2" property in > > the ICE device node. OPP-tabel is kept as an optional property. > > Last two lines are redundant. Instead explain the hardware - why it did > not support clock scaling before? Sure, will remove out redundant lines and update the commit message as requested. > > > > > Signed-off-by: Abhinaba Rakshit > > --- > > .../bindings/crypto/qcom,inline-crypto-engine.yaml | 29 ++++++++++++++++++++++ > > 1 file changed, 29 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml > > index c3408dcf5d2057270a732fe0e6744f4aa6496e06..1e849def1e0078feb45874a436411188d26cf37f 100644 > > --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml > > +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml > > @@ -30,6 +30,14 @@ properties: > > clocks: > > maxItems: 1 > > > > + operating-points-v2: > > + description: > > + Each OPP entry contains the frequency configuration for the ICE device > > + clock(s). > > Drop description, please look how other bindings define this. Sure, will check and update this.