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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?g009TCv3s932SA6Pk4KpCM8974k5S+zFttpxnQA+ZGnlnCCd/3bSNb+ttnRo?= =?us-ascii?Q?DqIVxMmJDXaG536Vv1He15Iv4LcFScziA1nDsmrC4uGJ4AMKACVMReBqbnOp?= =?us-ascii?Q?xNB7Hh3vIZYMoZsbjmmd5kwup/qOdU+jM16Y2CZ0KwdAuKqWsyr998i7+xJK?= =?us-ascii?Q?T3JZZKUMJi9E/Qz8dHjDorgm2GCHSHfSQi4edajeorQ4jW24aFtvain/WMM/?= =?us-ascii?Q?+ICOiNVgExC8JQcVY9+G8RAwNC18swmg4v8B/VJDi9E/z0lUcBpNxm99qKWd?= =?us-ascii?Q?7gNGXytTzCyq0DAo07X89U4o4ZnyG2/9KtVWHsNXcAYLjj8xGuH6fXmG12+o?= =?us-ascii?Q?o8L1iJKR813qp2AE6nuUhFifZPeOITj07S8CPZGICrA/IFc5KpgwSHIJOxTy?= =?us-ascii?Q?iEf8qsRkqVbHtconqM2Gl6kKaUeWCWVd+hbzIpcUkMariE5D8TZ1rVKTPCd8?= =?us-ascii?Q?AoAAuKZqci5xpl62d7cJCjjdXkYSJxECgZqbUthQ1VFlItCDGQGA8T0NEk11?= =?us-ascii?Q?FCA4Xjxtg1x5TEVYz6UlL8ZawMTgcdJMCwag5d2NpugolkYR5zbc4CC2Lc7d?= =?us-ascii?Q?De2EZj/f6m/zgC4OuW2h5IILSsmjk03t7zihZ1VOYi+iDLnnvxojfhl12t+6?= =?us-ascii?Q?QvF78NI/wkb2w+llV/rfXwcDY3dTVB8Zyq4s4jIZY9Fpg/LYPXf3cbmGY7Z9?= =?us-ascii?Q?wa8tza8DJJuNgp5s1eTS7g7lozOpjgnx4ZCw1NO5VpozZzbHiltCAJjM0AXM?= =?us-ascii?Q?oq2y2pmRTxLOTm5liFzUAfkWcwrQ+IHxKooGpt4Mfmt+HRDP0Iabaf49rQ65?= =?us-ascii?Q?ISJabkaCeWCRQ6ej84D/bXlsjYhhiQh51tQA7fj85c4P5Gq9Lz7LEta8DApp?= =?us-ascii?Q?hW37y1eZT+l06W3AfysBmp2mKADU/TkGgouQH6yvMfdk2y55XKR90Ynn9dGL?= =?us-ascii?Q?ic+EHwpg1AV/gzoS8BZAAROOqE6WqKv61aDxcajl8W75f6bLPvP/ewqt/LrZ?= =?us-ascii?Q?QXRZ9F74LyIb6Zw7sioeEg3LsFvRILb7x0UWa+GkCaLfn5vByof1FHiFKfFW?= =?us-ascii?Q?DWMnLTKuhhpdV5O5zslVauiIrgmvmkec3C5eWTY+nGKwSV0cKx1tZZxyogKa?= =?us-ascii?Q?a5Aga3UBQvlJnF7Sijamj8HG04FzVjzr31oM+ITYr0blCHD+eh0sHqnrPC5O?= =?us-ascii?Q?EUG6jvcxAwNp87LGfjMqRqezVnrjRL9quZ+ytj6xCkk5X6fJ9k37Zew2h/Wh?= =?us-ascii?Q?74J4SKRZVzJL0BHeoGxaKQufCRrH9loxqUXzjDCAIye0aJPd0+39ot+Bt0fs?= =?us-ascii?Q?XaqMUdg3MFM7OF2c8rlsQhhAoiHq9UeZLi3/Gsc9Qv4kkSaNFbnBT3NmRxOT?= =?us-ascii?Q?qbep3Bg3b423B4dVPCRmRKs142Ek4fIydPZ2UOt28pHv0RzW4lnkzWS7U/Tq?= =?us-ascii?Q?eBHgE8laWtfchyHptFBDk3ooM3cQ2B8f6D8PPqCDcXcPL+d3Hly6EXDDCy6m?= =?us-ascii?Q?ulvoH3HD+aW6Wwt5pxAZGZ1WngOkRecJHQPo+xQZuL70GKeNfBmN7+fK97VR?= =?us-ascii?Q?zP0YoDAbcfJvTzrkNfwPmYvN7jBSTepMA213+YvPy0mBmnfKuzJ8y5O4ISRz?= =?us-ascii?Q?JmyDDP3IBtLQb27k+tSIQ0fzacS1lW1TxbjGZ/YLg2t8C1at4qfg3R1HJenE?= =?us-ascii?Q?ThhVYbqkvp5aX9iPh2NvF5LyyCIaBsVbqZxaW3juppnEMozs?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 67fc7c32-fb35-440c-a3b0-08de748dd592 X-MS-Exchange-CrossTenant-AuthSource: PA4PR04MB9366.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Feb 2026 16:49:25.9302 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: J121H+SQzi4fgyiu+1aadT/+Nt+nFDavud8mEoXVptuSbizGGS7UAu79O+DYOQ5AOMhb1i98yy/Pq+KO4ipe+A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA1PR04MB12174 On Tue, Jan 20, 2026 at 03:33:30PM +0200, Claudiu wrote: > From: Claudiu Beznea > > Add support for device_{pause, resume}() callbacks. These are required by > the RZ/G2L SCIFA driver. "These are required by the RZ/G2L SCIFA driver", is not good enough. Can you descript why RZ/G2L SCIFA require it? Frank > > Signed-off-by: Claudiu Beznea > --- > > Changes in v8: > - reported residue for paused channels as well > > Changes in v7: > - use guard() instead of scoped_guard() > - in rz_dmac_device_pause() checked the channel is enabled > before suspending it to avoid read poll timeouts > - added a comment in rz_dmac_device_resume() > > Changes in v6: > - set CHCTRL_SETSUS for pause and CHCTRL_CLRSUS for resume > - dropped read-modify-update approach for CHCTRL updates as the > HW returns zero when reading CHCTRL > - moved the read_poll_timeout_atomic() under spin lock to > ensure avoid any races b/w pause and resume functionalities > > Changes in v5: > - used suspend capability of the controller to pause/resume > the transfers > > drivers/dma/sh/rz-dmac.c | 49 +++++++++++++++++++++++++++++++++++++--- > 1 file changed, 46 insertions(+), 3 deletions(-) > > diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c > index 27c963083e29..caa3335bf95d 100644 > --- a/drivers/dma/sh/rz-dmac.c > +++ b/drivers/dma/sh/rz-dmac.c > @@ -141,10 +141,12 @@ struct rz_dmac { > #define CHANNEL_8_15_COMMON_BASE 0x0700 > > #define CHSTAT_ER BIT(4) > +#define CHSTAT_SUS BIT(3) > #define CHSTAT_EN BIT(0) > > #define CHCTRL_CLRINTMSK BIT(17) > #define CHCTRL_CLRSUS BIT(9) > +#define CHCTRL_SETSUS BIT(8) > #define CHCTRL_CLRTC BIT(6) > #define CHCTRL_CLREND BIT(5) > #define CHCTRL_CLRRQ BIT(4) > @@ -814,11 +816,18 @@ static enum dma_status rz_dmac_tx_status(struct dma_chan *chan, > if (status == DMA_COMPLETE || !txstate) > return status; > > - scoped_guard(spinlock_irqsave, &channel->vc.lock) > + scoped_guard(spinlock_irqsave, &channel->vc.lock) { > + u32 val; > + > residue = rz_dmac_chan_get_residue(channel, cookie); > > - /* if there's no residue, the cookie is complete */ > - if (!residue) > + val = rz_dmac_ch_readl(channel, CHSTAT, 1); > + if (val & CHSTAT_SUS) > + status = DMA_PAUSED; > + } > + > + /* if there's no residue and no paused, the cookie is complete */ > + if (!residue && status != DMA_PAUSED) > return DMA_COMPLETE; > > dma_set_residue(txstate, residue); > @@ -826,6 +835,38 @@ static enum dma_status rz_dmac_tx_status(struct dma_chan *chan, > return status; > } > > +static int rz_dmac_device_pause(struct dma_chan *chan) > +{ > + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); > + u32 val; > + > + guard(spinlock_irqsave)(&channel->vc.lock); > + > + val = rz_dmac_ch_readl(channel, CHSTAT, 1); > + if (!(val & CHSTAT_EN)) > + return 0; > + > + rz_dmac_ch_writel(channel, CHCTRL_SETSUS, CHCTRL, 1); > + return read_poll_timeout_atomic(rz_dmac_ch_readl, val, > + (val & CHSTAT_SUS), 1, 1024, > + false, channel, CHSTAT, 1); > +} > + > +static int rz_dmac_device_resume(struct dma_chan *chan) > +{ > + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); > + u32 val; > + > + guard(spinlock_irqsave)(&channel->vc.lock); > + > + /* Do not check CHSTAT_SUS but rely on HW capabilities. */ > + > + rz_dmac_ch_writel(channel, CHCTRL_CLRSUS, CHCTRL, 1); > + return read_poll_timeout_atomic(rz_dmac_ch_readl, val, > + !(val & CHSTAT_SUS), 1, 1024, > + false, channel, CHSTAT, 1); > +} > + > /* > * ----------------------------------------------------------------------------- > * IRQ handling > @@ -1164,6 +1205,8 @@ static int rz_dmac_probe(struct platform_device *pdev) > engine->device_terminate_all = rz_dmac_terminate_all; > engine->device_issue_pending = rz_dmac_issue_pending; > engine->device_synchronize = rz_dmac_device_synchronize; > + engine->device_pause = rz_dmac_device_pause; > + engine->device_resume = rz_dmac_device_resume; > > engine->copy_align = DMAENGINE_ALIGN_1_BYTE; > dma_set_max_seg_size(engine->dev, U32_MAX); > -- > 2.43.0 >