From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6FCC1D88AC for ; Tue, 17 Feb 2026 15:00:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771340427; cv=none; b=Ai3ast3Umdo5Bvk7kxDWmlWaEG1mQsMNSOm+Do8AFyac+kfTBVV9HUrl3CQOQH3HPSssEltQ+gSZqKpzMYJohz+tukGvN6JAGRq/OmAw+oGirCKl6ucLdf7ozctQXWyEf4eDeznhyvi1SnFh9U4XW+wTgjagXPgJZTBdtC6pn0k= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771340427; c=relaxed/simple; bh=mYlEGTrnI5a+ac/YZf3DtKWdXwxsXj53TyqIoLRWIzo=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=iVC5tZ5N0r+iKORvoS3HGPAidF6ortZd4Jl15r8qyUQJPbJlmKPPpVawNzvkBs4Lm9k+Awqbqxi6csXxTZmO5BL9TpBoB4asbyW3kDmHHrZw9QfmsCXjWiWMQ90jtBJP1213MXRpy6ANb7yCOq0XLcdomOP3gUGCvwpitW+hDz4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=khSwFnha; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="khSwFnha" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3F859C4CEF7; Tue, 17 Feb 2026 15:00:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771340427; bh=mYlEGTrnI5a+ac/YZf3DtKWdXwxsXj53TyqIoLRWIzo=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=khSwFnhaKqZ5o63eBjO0BzLXJRawh6pmStxVUPeTAIXZZlhUpuP+8YcjmjMN29hPl Yl7K5CpRYSFIKjMqvNFAcQcLM3JtyH3v47JGgKix7BLh+AweL9xdx8A7YfagpEWPcy WPZ8gldWsd1HAUchXt4wKOvRtrVLQWTuES1Friu7VhYqjPclFcwkCSCTF4ferGwzdl y/On8mjRubMqmu5d9CDhKQOYznD33kNE/LYRTBUF9GANF2jwzhhXaqd5DB7fsREcCQ fKFSsLE0u6XfBm+URlTQtKijNecsKbEBg6Ncw3myuhC3nkzklTRSO9p2lfVYcYaFXT rj4ICINQ3lyBw== Date: Tue, 17 Feb 2026 15:00:22 +0000 From: Will Deacon To: Catalin Marinas Cc: Dev Jain , Jisheng Zhang , Dennis Zhou , Tejun Heo , Christoph Lameter , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, maz@kernel.org Subject: Re: [PATCH] arm64: remove HAVE_CMPXCHG_LOCAL Message-ID: References: <20260215033944.16374-1-jszhang@kernel.org> <89606308-3c03-4dcf-a89d-479258b710e4@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Feb 17, 2026 at 01:53:19PM +0000, Catalin Marinas wrote: > On Mon, Feb 16, 2026 at 08:59:17PM +0530, Dev Jain wrote: > > On 16/02/26 4:30 pm, Will Deacon wrote: > > > On Sun, Feb 15, 2026 at 11:39:44AM +0800, Jisheng Zhang wrote: > > >> It turns out the generic disable/enable irq this_cpu_cmpxchg > > >> implementation is faster than LL/SC or lse implementation. Remove > > >> HAVE_CMPXCHG_LOCAL for better performance on arm64. > > >> > > >> Tested on Quad 1.9GHZ CA55 platform: > > >> average mod_node_page_state() cost decreases from 167ns to 103ns > > >> the spawn (30 duration) benchmark in unixbench is improved > > >> from 147494 lps to 150561 lps, improved by 2.1% > > >> > > >> Tested on Quad 2.1GHZ CA73 platform: > > >> average mod_node_page_state() cost decreases from 113ns to 85ns > > >> the spawn (30 duration) benchmark in unixbench is improved > > >> from 209844 lps to 212581 lps, improved by 1.3% > > >> > > >> Signed-off-by: Jisheng Zhang > > >> --- > > >> arch/arm64/Kconfig | 1 - > > >> arch/arm64/include/asm/percpu.h | 24 ------------------------ > > >> 2 files changed, 25 deletions(-) > > > That is _entirely_ dependent on the system, so this isn't the right > > > approach. I also don't think it's something we particularly want to > > > micro-optimise to accomodate systems that suck at atomics. > > > > Hi Will, > > > > As I mention in the other email, the suspect is not the atomics, but > > preempt_disable(). On Apple M3, the regression reported in [1] resolves > > by removing preempt_disable/enable in _pcp_protect_return. To prove > > this another way, I disabled CONFIG_ARM64_HAS_LSE_ATOMICS and the > > regression worsened, indicating that at least on Apple M3 the > > atomics are faster. > > Then why don't we replace the preempt disabling with local_irq_save() > in the arm64 code and still use the LSE atomics? Even better, work on making preempt_disable() faster as it's used in many other places. Of course, if people want to hack the .config, they could also change the preemption mode... Will