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Only used when xlnx,axistream-connected > + is present (DMA connected to AXI Stream IP). One interrupt for single channel > + (MM2S or S2MM), two interrupts for dual channel configuration. > + When child dma-channel nodes are present, interrupts are specified in the > + child nodes instead. interrupts items: - description: for single channel - description: for dual channel minItems: 1 > + > + clocks: > + minItems: 1 > + maxItems: 5 > + > + clock-names: > + minItems: 1 > + maxItems: 5 > + > + dma-ranges: true > + > + xlnx,addrwidth: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [32, 64] > + description: The DMA addressing size in bits. > + > + xlnx,num-fstores: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 1 > + maximum: 32 > + description: Should be the number of framebuffers as configured in h/w. > + > + xlnx,flush-fsync: > + type: boolean > + description: Tells which channel to Flush on Frame sync. > + > + xlnx,sg-length-width: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 8 > + maximum: 26 > + default: 23 > + description: > + Should be set to the width in bits of the length register as configured > + in h/w. Takes values {8...26}. If the property is missing or invalid then > + the default value 23 is used. This is the maximum value that is supported > + by all IP versions. > + > + xlnx,irq-delay: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 255 > + description: > + Tells the interrupt delay timeout value. Valid range is from 0-255. > + Setting this value to zero disables the delay timer interrupt. > + 1 timeout interval = 125 * clock period of SG clock. > + > + xlnx,axistream-connected: > + type: boolean > + description: Tells whether DMA is connected to AXI stream IP. > + > +# Note: This schema combines all DMA types in one file. Parent-child channel > +# compatibility is enforced via allOf conditionals below. Alternatively, this > +# could be split into separate schemas per DMA type to simplify validation rules. > +patternProperties: > + "^dma-channel(-mm2s|-s2mm)?$": > + type: object > + description: > + Should have at least one channel and can have up to two channels per > + device. This node specifies the properties of each DMA channel. > + > + properties: > + compatible: > + enum: > + - xlnx,axi-vdma-mm2s-channel > + - xlnx,axi-vdma-s2mm-channel > + - xlnx,axi-cdma-channel > + - xlnx,axi-dma-mm2s-channel > + - xlnx,axi-dma-s2mm-channel > + > + interrupts: > + maxItems: 1 > + > + xlnx,datawidth: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [32, 64, 128, 256, 512, 1024] > + description: Should contain the stream data width, take values {32,64...1024}. > + > + xlnx,include-dre: > + type: boolean > + description: Tells hardware is configured for Data Realignment Engine. > + > + xlnx,genlock-mode: > + type: boolean > + description: Tells Genlock synchronization is enabled/disabled in hardware. > + > + xlnx,enable-vert-flip: > + type: boolean > + description: > + Tells vertical flip is enabled/disabled in hardware(S2MM path). > + > + dma-channels: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: Number of dma channels in child node. > + > + required: > + - compatible > + - interrupts > + - xlnx,datawidth > + > + additionalProperties: false > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: xlnx,axi-vdma-1.00.a > + then: > + properties: > + clock-names: > + contains: > + const: s_axi_lite_aclk > + items: > + enum: > + - s_axi_lite_aclk > + - m_axi_mm2s_aclk > + - m_axi_s2mm_aclk > + - m_axis_mm2s_aclk > + - s_axis_s2mm_aclk > + minItems: 1 > + maxItems: 5 > + patternProperties: > + "^dma-channel(-mm2s|-s2mm)?$": > + properties: > + compatible: > + enum: > + - xlnx,axi-vdma-mm2s-channel > + - xlnx,axi-vdma-s2mm-channel > + required: > + - xlnx,num-fstores > + > + - if: > + properties: > + compatible: > + contains: > + const: xlnx,axi-cdma-1.00.a > + then: > + properties: > + clock-names: > + items: > + - const: s_axi_lite_aclk > + - const: m_axi_aclk > + patternProperties: > + "^dma-channel(-mm2s|-s2mm)?$": > + properties: > + compatible: > + enum: > + - xlnx,axi-cdma-channel > + > + - if: > + properties: > + compatible: > + contains: > + anyOf: > + - const: xlnx,axi-dma-1.00.a > + - const: xlnx,axi-mcdma-1.00.a > + then: > + properties: > + clock-names: > + contains: > + const: s_axi_lite_aclk > + items: > + enum: > + - s_axi_lite_aclk > + - m_axi_mm2s_aclk > + - m_axi_s2mm_aclk > + - m_axi_sg_aclk > + minItems: 1 > + maxItems: 4 > + patternProperties: > + "^dma-channel(-mm2s|-s2mm)?(@[0-9a-f]+)?$": > + properties: > + compatible: > + enum: > + - xlnx,axi-dma-mm2s-channel > + - xlnx,axi-dma-s2mm-channel > + > + - if: > + anyOf: > + - properties: > + compatible: > + contains: > + anyOf: > + - const: xlnx,axi-cdma-1.00.a > + - const: xlnx,axi-mcdma-1.00.a > + - const: xlnx,axi-dma-1.00.a > + then: > + properties: > + interrupts: false > + > +required: > + - "#dma-cells" > + - reg > + - xlnx,addrwidth > + - dma-ranges > + - clocks > + - clock-names > + > +additionalProperties: false need ref dma-controller.yaml > + > +examples: > + - | > + #include > + > + axi_vdma_0: dma@40030000 { Needn't label axi_vdma_0 > + compatible = "xlnx,axi-vdma-1.00.a"; > + #dma-cells = <1>; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x40030000 0x10000>; > + dma-ranges = <0x0 0x0 0x40000000>; > + xlnx,num-fstores = <8>; > + xlnx,flush-fsync; > + xlnx,addrwidth = <32>; > + clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>; > + clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", > + "m_axi_s2mm_aclk", "m_axis_mm2s_aclk", > + "s_axis_s2mm_aclk"; > + > + dma-channel-mm2s { > + compatible = "xlnx,axi-vdma-mm2s-channel"; > + interrupts = ; > + xlnx,datawidth = <64>; > + }; > + > + dma-channel-s2mm { > + compatible = "xlnx,axi-vdma-s2mm-channel"; > + interrupts = ; > + xlnx,datawidth = <64>; > + }; > + }; > -- > 2.25.1 >