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Wed, 18 Dec 2024 07:25:29 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BI7PSAe002277 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2024 07:25:28 GMT Received: from [10.253.15.72] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 17 Dec 2024 23:25:25 -0800 Message-ID: Date: Wed, 18 Dec 2024 15:25:22 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: qcs615-ride: Enable ethernet node To: Andrew Lunn CC: Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , , , , References: <2556b02c-f884-40c2-a0d4-0c87da6e5332@quicinc.com> <75fb42cc-1cc5-4dd3-924c-e6fda4061f03@quicinc.com> <4a6a6697-a476-40f4-b700-09ef18e4ba22@lunn.ch> <441f37f5-3c33-4c62-b3fe-728b43669e29@quicinc.com> <4287c838-35b2-45bb-b4a2-e128b55ddbaf@lunn.ch> <2e518360-be24-45d8-914d-1045c6771620@quicinc.com> <31a87bd9-4ffb-4d5a-a77b-7411234f1a03@lunn.ch> <581776bc-f3bc-44c1-b7c0-4c2e637fcd67@quicinc.com> <174bd1a3-9faf-4850-b341-4a4cce1811cb@lunn.ch> <8acf4557-ac10-43f1-b1ab-7ae63f64401f@lunn.ch> Content-Language: en-US From: Yijie Yang In-Reply-To: <8acf4557-ac10-43f1-b1ab-7ae63f64401f@lunn.ch> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: A4ZjIu75VbPGB7_ca6tBmQcOQdnuVuo8 X-Proofpoint-GUID: A4ZjIu75VbPGB7_ca6tBmQcOQdnuVuo8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=899 bulkscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412180058 On 2024-12-17 18:18, Andrew Lunn wrote: > On Tue, Dec 17, 2024 at 10:26:15AM +0800, Yijie Yang wrote: >> >> >> On 2024-12-16 17:18, Andrew Lunn wrote: >>>> I intend to follow these steps. Could you please check if they are correct? >>>> 1. Add a new flag in DTS to inform the MAC driver to include the delay when >>>> configured with 'rgmii-id'. Without this flag, the MAC driver will not be >>>> aware of the need for the delay. >>> >>> Why do you need this flag? >>> >>> If the phy-mode is rgmii-id, either the MAC or the PHY needs to add >>> the delay. >>> >>> The MAC driver gets to see phy-mode first. If it wants to add the >>> delay, it can, but it needs to mask out the delays before passing >>> phy-mode to the PHY. If the MAC driver does not want to add the >>> delays, pass phy-mode as is the PHY, and it will add the delays. >> >> In this scenario, the delay in 'rgmii-id' mode is currently introduced by >> the MAC as it is fixed in the driver code. How can we enable the PHY to add >> the delay in this mode in the future (If we intend to revert to the most >> common approach of the Linux kernel)? After all, the MAC driver is unsure >> when to add the delay. > > You just take out the code in the MAC driver which adds the delay and > masks the phy-mode. 2ns should be 2ns delay, independent of who > inserts it. The only danger is, there might be some board uses a PHY > which is incapable of adding the 2ns delay, and such a change breaks > that board. Okay, I will follow your instructions: 1. Change the phy-mode to 'rgmii-id'. 2. Add the delay in the MAC driver. 3. Mask the phy-mode before passing it to the PHY. > > But i assume Qualcomm RDKs always make use of a Qualcomm PHY, there is > special pricing if you use the combination, so there is probably > little incentive to use somebody elses PHY. And i assume you can > quickly check all Qualcomm PHYs support RGMII delays. PHYs which don't > support RGMII delays are very rare, it just happened that one vendors > RDK happened to use one, so they ended up with delays in the MAC being > standard for their boards. > Most Qualcomm MAC applications are actually paired with a third-party PHY. I agree that the original author's PHY might not support adding the delay. However, this assumption cannot be verified since the initial code was uploaded from the internal code base. > Andrew > -- Best Regards, Yijie