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Thu, 23 Oct 2025 17:04:14 -0700 (PDT) Message-ID: Date: Thu, 23 Oct 2025 19:04:14 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 6/9] spi: fsl-qspi: allot 1KB per chip To: Frank Li Cc: han.xu@nxp.com, broonie@kernel.org, dlan@gentoo.org, guodong@riscstar.com, linux-spi@vger.kernel.org, imx@lists.linux.dev, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20251023175922.528868-1-elder@riscstar.com> <20251023175922.528868-7-elder@riscstar.com> Content-Language: en-US From: Alex Elder In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 10/23/25 6:38 PM, Frank Li wrote: > On Thu, Oct 23, 2025 at 12:59:18PM -0500, Alex Elder wrote: >> In fsl_qspi_default_setup(), four registers define the size of blocks of >> data to written to each of four chips that comprise SPI NOR flash storage. >> They are currently defined to be the same as the AHB buffer size (which is >> always 1KB). >> >> The SpacemiT QSPI has an AHB buffer size of 512 bytes, but requires these >> four sizes to be multiples of 1024 bytes. >> >> Define a new field sfa_size in the fsl_qspi_devtype_data structure that, if >> non-zero, will be used instead of the AHB buffer size to define the size of >> these chip regions. >> >> Signed-off-by: Alex Elder >> --- >> v2: - New field fsl_qspi_devtype_data->sfa_size now defines the size of >> the serial flash regions if it's non-zero >> >> drivers/spi/spi-fsl-qspi.c | 22 ++++++++++++---------- >> 1 file changed, 12 insertions(+), 10 deletions(-) >> >> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c >> index c21e3804cb032..a474d1b341b6a 100644 >> --- a/drivers/spi/spi-fsl-qspi.c >> +++ b/drivers/spi/spi-fsl-qspi.c >> @@ -207,6 +207,7 @@ struct fsl_qspi_devtype_data { >> unsigned int txfifo; >> int invalid_mstrid; >> unsigned int ahb_buf_size; >> + unsigned int sfa_size; >> unsigned int quirks; >> bool little_endian; >> }; >> @@ -737,6 +738,7 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q) >> { >> void __iomem *base = q->iobase; >> u32 reg, addr_offset = 0; >> + u32 size; > > I think use 'sfa_size' is better to read code. OK I'll rename in the next version. Thanks. -Alex > Reviewed-by: Frank Li >> int ret; >> >> /* disable and unprepare clock to avoid glitch pass to controller */ >> @@ -795,17 +797,17 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q) >> * In HW there can be a maximum of four chips on two buses with >> * two chip selects on each bus. We use four chip selects in SW >> * to differentiate between the four chips. >> - * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD, >> - * SFB2AD accordingly. >> + * >> + * By default we write the AHB buffer size to each chip, but >> + * a different size can be specified with devtype_data->sfa_size. >> + * The SFA1AD, SFA2AD, SFB1AD, and SFB2AD registers define the >> + * top (end) of these four regions. >> */ >> - qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset, >> - base + QUADSPI_SFA1AD); >> - qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset, >> - base + QUADSPI_SFA2AD); >> - qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset, >> - base + QUADSPI_SFB1AD); >> - qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset, >> - base + QUADSPI_SFB2AD); >> + size = q->devtype_data->sfa_size ? : q->devtype_data->ahb_buf_size; >> + qspi_writel(q, addr_offset + 1 * size, base + QUADSPI_SFA1AD); >> + qspi_writel(q, addr_offset + 2 * size, base + QUADSPI_SFA2AD); >> + qspi_writel(q, addr_offset + 3 * size, base + QUADSPI_SFB1AD); >> + qspi_writel(q, addr_offset + 4 * size, base + QUADSPI_SFB2AD); >> >> q->selected = -1; >> >> -- >> 2.43.0 >>