Re: [PATCH v7.1 2/4] gpu: nova-core: bitfield: Move bitfield-specific code from register! into new macro

[John Hubbard <jhubbard@nvidia.com>]

On 10/16/25 12:39 PM, John Hubbard wrote:
> On 10/16/25 12:34 PM, Danilo Krummrich wrote:
>> On Thu Oct 16, 2025 at 9:28 PM CEST, Joel Fernandes wrote:
>>>> On Oct 16, 2025, at 1:48 PM, Yury Norov <yury.norov@gmail.com> wrote:
>>>> On Thu, Oct 16, 2025 at 11:13:21AM -0400, Joel Fernandes wrote:
> ...
>> While I'm not super opinionated for general bitfields, for the register!()
>> infrastructure I very much prefer the hi:lo notation, as this is the common
>> notation in datasheets and TRMs.
>>
>> However, if we use hi:lo, we should use it decending, i.e.:
(restored from the email thread):

	bitfield! {
	    struct ControlReg {
	        7:5 state as u8 => State;
	        3:0 mode as u8 ?=> Mode;
	    }
	}>>
> 
> Sure, descending works.

Oops! I need to correct myself. After reviewing most of Joel Fernandes'
latest patchset ([PATCH 0/7] Pre-requisite patches for mm and irq in
nova-core) [1], I remember that the HW documentation is written in
ascending order.

For one example (out of countless hundreds or thousands), please see [2].
Considering that I actually pushed this file up to github just a few
years ago, it's rather silly of me to forget this basic truth. :)

We really want to stay close to the HW documentation, and so, all other
things being (nearly) equal, this means that we should prefer ascending
field order, if that's OK with everyone.


[1] https://lore.kernel.org/20251020185539.49986-1-joelagnelf@nvidia.com
[2] https://github.com/NVIDIA/open-gpu-doc/blob/master/manuals/ampere/ga102/dev_ce.ref.txt

thanks,
-- 
John Hubbard