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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8fc735e587sm541749566b.2.2026.02.19.01.29.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Feb 2026 01:29:35 -0800 (PST) Message-ID: Date: Thu, 19 Feb 2026 10:29:33 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] arm64: dts: qcom: sm8550: add OSM L3 node and cpu interconnect nodes To: webgeek1234@gmail.com, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Georgi Djakov , Sibi Sankar Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org References: <20260218-sm8550-ddr-bw-scaling-v2-0-43a2b6d47e70@gmail.com> <20260218-sm8550-ddr-bw-scaling-v2-2-43a2b6d47e70@gmail.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260218-sm8550-ddr-bw-scaling-v2-2-43a2b6d47e70@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: N7dYhqFuWVgbZ8mNYzDsyVw8B2ogq09h X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE5MDA4NiBTYWx0ZWRfXxUfOAUx3u18D jttp6Fqi5rbSxM4Yx7tIssv31crQBMIXnN0HPbvlz84LDVrVjC8/kaKZrtBMo0MQb72alUqSQtJ fhzV1c9E0q8cgbJAsVdDI/YhQwAqph1fPmO+aQhLqapmPAo/8/YjXT3YoH0ptqT/g4v8SLjUFGS O+hudNWBJC4L6llZMYMeB13Y35/ClpnO4AXVPDzedwrYZeNsAKwUdVvkiNnA1N0k/ReH5QW27cg sPMl1mM4whjHjiV5i9/JZwf2FYQikuKoqA8mpklNE3zDctOtbjGEgU4iYqtWgqo2ivjX5CnFee5 tNsKLF54TWRmgcskrlTyzJRd6EctwINiH9fsP82F5s3ZBDPQIbMiT64eRPQNUu0yh8KBhXbrBRo DM9/WuG6QqykOmrSV4PIwZeKWwWK/E1k1q+6GdeMsR50FchkYtAxW8lOFlmJa6fFYW0fTEfB2ee /7JGjT5jRVFl3MIfW6w== X-Proofpoint-GUID: N7dYhqFuWVgbZ8mNYzDsyVw8B2ogq09h X-Authority-Analysis: v=2.4 cv=W/M1lBWk c=1 sm=1 tr=0 ts=6996d801 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=pGLkceISAAAA:8 a=hU_naWAkiL-jcIhTA_oA:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-19_02,2026-02-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 adultscore=0 malwarescore=0 clxscore=1015 suspectscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602190086 On 2/18/26 7:16 PM, Aaron Kling via B4 Relay wrote: > From: Aaron Kling > > Add the OSC L3 Cache controller node. > > Also add the interconnect entry for each cpu, with 3 different paths: > - CPU to Last Level Cache Controller (LLCC) > - Last Level Cache Controller (LLCC) to DDR > - L3 Cache from CPU to DDR interface > > Signed-off-by: Aaron Kling > --- This should still be squashed with patch 3, as while you wire up the CPUs as interconnect consumers, they cast no vote, leading to the situation Krzysztof mentioned where the performance actually majorly goes *down*, since the icc core sees no users present and assumes it can send a zero-vote (which probably translates to F_MIN for the cache) Konrad