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Tue, 10 Dec 2024 10:12:16 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BAACFwu000891 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 10 Dec 2024 10:12:15 GMT Received: from [10.216.28.232] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 10 Dec 2024 02:12:11 -0800 Message-ID: Date: Tue, 10 Dec 2024 15:42:07 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] dt-bindings: usb: snps,dwc3: Add snps,filter-se0-fsls-eop quirk From: Krishna Kurapati To: Krzysztof Kozlowski , Uttkarsh Aggarwal , Thinh Nguyen CC: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Greg Kroah-Hartman , Felipe Balbi , Thinh Nguyen , , , , , References: <20241017114055.13971-1-quic_uaggarwa@quicinc.com> <20241017114055.13971-2-quic_uaggarwa@quicinc.com> <1129e0a7-6bd0-416e-8c56-6b8d75600c4e@quicinc.com> <99810132-85b6-45ee-9933-7a00c3672c47@quicinc.com> Content-Language: en-US In-Reply-To: <99810132-85b6-45ee-9933-7a00c3672c47@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: UY41v4HwgMP5vdunX35jyK2vr4GVxLh2 X-Proofpoint-GUID: UY41v4HwgMP5vdunX35jyK2vr4GVxLh2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 priorityscore=1501 mlxlogscore=733 clxscore=1015 mlxscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412100076 On 11/20/2024 2:53 PM, Krishna Kurapati wrote: > > > On 11/7/2024 3:25 PM, Krzysztof Kozlowski wrote: >> On 07/11/2024 07:17, Krishna Kurapati wrote: >>> >>> >>> On 10/18/2024 11:57 AM, Krzysztof Kozlowski wrote: >>>> On Thu, Oct 17, 2024 at 05:10:54PM +0530, Uttkarsh Aggarwal wrote: >>>>> Adding a new 'snps,filter-se0-fsls-eop quirk' DT quirk to dwc3 core >>>>> to set >>>>> GUCTL1 BIT 29. When set, controller will ignore single SE0 glitch >>>>> on the >>>>> linestate during transmission. Only two or more SE0 is considered as >>>>> valid EOP on FS/LS port. This bit is applicable only in FS in >>>>> device mode >>>>> and FS/LS mode of operation in host mode. >>>> >>>> Why this is not device/compatible specific? Just like all other quirks >>>> pushed last one year. >>> >>> Hi Krzysztof, >>> >>>    Apologies for a late reply from our end. >>> >>>    In DWC3 core/dwc3-qcom atleast, there have been no compatible >>> specific >>> quirks added. >> > > Sorry again for late reply. > >> Nothing stops from adding these, I think. >> > > Agree, we can take that approach of adding soc specific compatibles to > dwc3 driver instead of adding through bindings. > >>> Also since this is a property of the Synopsys controller >>> hardware and not QC specific one, can we add it in bindings itself. >>> Because this is a property other vendors might also use and adding it >>> via compatible might not be appropriate. >> >> This does no answer my question. I don't see how this is not related to >> one specific piece of SoC. >> >> If you claim this is board-related, not SoC, give some arguments. >> Repeating the same is just no helping. >> > > But my point was that although the issue was found only on some QC > SoC's, the solution still lies in some bits being set in controller > register space and it is part of Synopsys IP. So wouldn't officially we > add that support in bindings and then enable/disable the feature via DT > like we did for other quirks ? If many SoC's need it in future, the > driver needs to add a long list of compatible specific data which > otherwise might be quirks in DT. > Hi Krzysztof, Gentle ping to provide your feedback on the last comment. Regards, Krishna,