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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ae83f7837bsm109166685ad.48.2026.03.09.02.08.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Mar 2026 02:08:47 -0700 (PDT) Date: Mon, 9 Mar 2026 14:38:41 +0530 From: Vishnu Saini To: Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, prahlad.valluru@oss.qualcomm.com, Prahlad Valluru Subject: Re: [PATCH v3 1/2] arm64: dts: qcom: monaco: add lt8713sx bridge with displayport Message-ID: References: <20251228-lt8713sx-bridge-linux-for-next-v3-0-3f77ad84d7d1@oss.qualcomm.com> <20251228-lt8713sx-bridge-linux-for-next-v3-1-3f77ad84d7d1@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Proofpoint-ORIG-GUID: IXslygHL72iQ5W3dvQbuSljDCXpk054b X-Proofpoint-GUID: IXslygHL72iQ5W3dvQbuSljDCXpk054b X-Authority-Analysis: v=2.4 cv=OOQqHCaB c=1 sm=1 tr=0 ts=69ae8e21 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=kx1GuS1i06gOX_RaChsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA5MDA4NCBTYWx0ZWRfX3mkWE+l/Slmp rPbV+S3FXTgSPUtEca7QW0m4F6Hh6zRArdLD2w4ednqSDgZ970INm/e9SVZcFMmANV/8ccZwd+9 YOs4KnxlDjPjzoFzwF+K6zsNOPms2P8k6du7FoclGxVb2N4C56EKxK9tSbgRVRYpuGuPkbO9US8 TK68IOQ4xBQn4Jk4JbaYUn+/At/j4Ghq1huf8u6+ZgQCN+0TwDlNAHuVttTwrAeDFZxML6vSCP+ zAsuA6qPRM4Rlb61mwUuSArq58YwxH7uatGotxFjE4d2z4SmEED9eNFtA8ujN+Bz/SHBRgbuGT6 JRVyEgJ6Lp8gVeE2VSfIs+XJzfVCFjzHfWaIB02aQlqCnRyZhuqvpA4xvQ0R7JaafVakLe8lx+H 3de7IIc40YzWbKm3lWHkWrLtGtb8nAEE1PKgZG60+aBCr6cx7k41ZOJ8rxun3B3jTxdiFzFbi/8 iivBzsWTzdmPRQ2iaOw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-09_03,2026-03-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603090084 On Sun, Feb 22, 2026 at 09:16:54PM +0200, Dmitry Baryshkov wrote: > On Sun, Feb 22, 2026 at 04:56:45AM +0530, Vishnu Saini wrote: > > On Sun, Dec 28, 2025 at 05:49:30PM +0200, Dmitry Baryshkov wrote: > > > On Sun, Dec 28, 2025 at 07:10:38PM +0530, Vishnu Saini wrote: > > > > Monaco-evk has LT8713sx which act as DP to 3 DP output > > > > converter. Edp PHY from monaco soc is connected to lt8713sx > > > > as input and output of lt8713sx is connected to 3 mini DP ports. > > > > > > > > Two ports are available in mainboard and one port > > > > is available on Mezz board. > > > > > > > > lt8713sx is connected to soc over i2c0 and with reset gpio > > > > connected to pin6 of ioexpander5. > > > > > > > > Enable the edp nodes from monaco and enable lontium lt8713sx > > > > bridge node. > > > > > > > > Co-developed-by: Prahlad Valluru > > > > Signed-off-by: Prahlad Valluru > > > > Signed-off-by: Vishnu Saini > > > > --- > > > > arch/arm64/boot/dts/qcom/monaco-evk.dts | 89 +++++++++++++++++++++++++++++++++ > > > > arch/arm64/boot/dts/qcom/monaco.dtsi | 6 +++ > > > > 2 files changed, 95 insertions(+) > > > > > > > > > > > @@ -396,10 +456,39 @@ expander6: gpio@3e { > > > > }; > > > > }; > > > > > > > > +&mdss { > > > > + status = "okay"; > > > > +}; > > > > + > > > > +&mdss_dp0 { > > > > + pinctrl-0 = <&dp_hot_plug_det>; > > > > + pinctrl-names = "default"; > > > > > > Is there a single HPD? How does it work? What happens if either of > > > connected displays sends a HPD pulse signal? > > > > Yes, from the SoC’s point of view there is a single HPD. > > LT8713SX aggregates multiple downstream HPDs from connected displays into one upstream HPD to soc. > > When any display is connected, the bridge firmware notices that one downstream port changed state and > > It aggregates a single HPD to soc. The SoC treats this as a DP interrupt and AUX transactions start. > > Are HPD Pulse IRQs also combined? yes, HPD Pulse IRQs are also combined. The bridge behaviour is similar to DP MST dongles. When any display is asserted, SOC will receive a short IRQ pulse and performs AUX/DPCD transactions to determines SST/MST topology. > > > > > > + > > > > + status = "okay"; > > > > +}; > > > > + > > > > +&mdss_dp0_out { > > > > + data-lanes = <0 1 2 3>; > > > > + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; > > > > + remote-endpoint = <<8713sx_dp_in>; > > > > > > Does the bridge use DP signalling or does it use USB-C signalling here? > > > And even if it is DP signalling, it should be correctly described as > > > it uses signals coming from the QMP PHY. See how it's done for laptops > > > with DP-HDMI convertors. > > Yes, the LT8713SX is using native DP signalling, not USB‑C DP Alt‑Mode. > > The QMP DP PHY is already implicitly part of the mdss_dp0 pipeline, > > similar to other Qualcomm platforms where external DP bridges are connected. Because of that, I intentionally modeled the connection as: > > MDSS DP controller -> LT8713SX bridge > > This keeps the DT consistent with existing Qualcomm DP bridge descriptions, where the PHY is not represented as a separate graph endpoint unless there is external lane muxing or alternative signalling paths. > > If you feel strongly that the DT should explicitly model: > > MDSS DP controller -> QMP DP PHY → LT8713SX bridge > > I can update the graph accordingly. Otherwise, please let me know if documenting this more clearly in the binding or commit message would be sufficient. > > Please check how (and why) other boards handle the similar usecase of > DP-to-HDMI bridges. To put it short, in your DT there is no notion that > it is a native DP rather than USB-C signalling. Sorry i couldn't find any good reference for DP-HDMI bridges to check signaling. I checked these DP-HDMI bridges PS175, PS176, PS186, PS195, PS196, RTD2171, RTD2142, TI DP159, VM5200 but none of them wire DT graph endpoints, Please let me know if there are any specific DP-HDMI bridge you are referring to. I looked for other references where USB‑C signaling is used, in those case the datapath always involves a USB‑C controller/Type‑C mux/switch explicitly represented in the DT. For native DP signaling, the common pattern is that the DP controller output is wired directly to a DP connector/bridge, without any UCB‑C components in the path. > > > > > > +}; > > > > + > > > > +&mdss_dp0_phy { > > > > + vdda-phy-supply = <&vreg_l5a>; > > > > + vdda-pll-supply = <&vreg_l4a>; > > > > + > > > > + status = "okay"; > > > > +}; > > > > + > > -- > With best wishes > Dmitry