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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Mike Leach <mike.leach@linaro.org>,
	Tingwei Zhang <tingweiz@codeaurora.org>
Cc: Coresight ML <coresight@lists.linaro.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: [RFC 00/11] arm64: coresight: Enable ETE and TRBE
Date: Mon, 23 Nov 2020 09:10:00 +0530	[thread overview]
Message-ID: <aa859d04-8ccf-cb4b-9ae4-524ab7c8451f@arm.com> (raw)
In-Reply-To: <CAJ9a7ViiZHi92Wr1uurb0B_nE4SmeHmbMChutaS++=FxcC8DTw@mail.gmail.com>

Hello Mike,

On 11/16/20 8:30 PM, Mike Leach wrote:
> Hi Anshuman,
> 
> I've not looked in detail at this set yet, but having skimmed through
> it  I do have an initial question about the handling of wrapped data
> buffers.
> 
> With the ETR/ETB we found an issue with the way perf concatenated data
> captured from the hardware buffer into a single contiguous data
> block. The issue occurs when a wrapped buffer appears after another
> buffer in the data file. In a typical session perf would stop trace
> and copy the hardware buffer multiple times into the auxtrace buffer.

The hardware buffer and perf aux trace buffer are the same for TRBE and
hence there is no actual copy involved. Trace data gets pushed into the
user space via perf_aux_output_end() either via etm_event_stop() or via
the IRQ handler i.e arm_trbe_irq_handler(). Data transfer to user space
happens via updates to perf aux buffer indices i.e head, tail, wake up.
But logically, they will appear as a stream of records to the user space
while parsing perf.data file.

> 
> e.g.
> 
> For ETR/ETB we have a fixed length hardware data buffer - and no way
> of detecting buffer wraps using interrupts as the tracing is in
> progress.

TRBE has an interrupt. Hence there will be an opportunity to insert any
additional packets if required to demarcate pre and post IRQ trace data
streams. 

> 
> If the buffer is not full at the point that perf transfers it then the
> data will look like this:-
> 1) <async><synced trace data>
> easy to decode, we can see the async at the start of the data - which
> would be the async issued at the start of trace.

Just curious, what makes the tracer to generate the <async> trace packet.
Is there an explicit instruction or that is how the tracer starts when
enabled ?

> 
> If the buffer wraps we see this:-
> 
> 2) <unsynced trace data><async><synced trace data>
> 
> Again no real issue, the decoder will skip to the async and trace from
> there - we lose the unsynced data.

Could you please elaborate more on the difference between sync and async
trace data ?

> 
> Now the problem occurs when multiple transfers of data occur. We can
> see the following appearing as contiguous trace in the auxtrace
> buffer:-
> 
> 3) < async><synced trace data><unsynced trace data><async><synced trace data>

So there is an wrap around event between <synced trace data> and
<unsynced trace data> ? Are there any other situations where this
might happen ?

> 
> Now the decoder cannot spot the point that the synced data from the
> first capture ends, and the unsynced data from the second capture
> begins.

Got it.

> This means it will continue to decode into the unsynced data - which
> will result in incorrect trace / outright errors. To get round this
> for ETR/ETB the driver will insert barrier packets into the datafile
> if a wrap event is detected.

But you mentioned there are on IRQs on ETR/ETB. So how the wrap event
is even detected ?

> 
> 4) <async><synced trace data><barrier><unsynced trace
> data><async><synced trace data>
> 
> This <barrier> has the effect of resetting the decoder into the
> unsynced state so that the invalid trace is not decoded. This is a
> workaround we have to do to handle the limitations of the ETR / ETB
> trace hardware.
Got it.

> 
> For TRBE we do have interrupts, so it should be possible to prevent
> the buffer wrapping in most cases - but I did see in the code that
> there are handlers for the TRBE buffer wrap management event. Are
> there other factors in play that will prevent data pattern 3) from
> appearing in the auxtrace buffer ?

On TRBE, the buffer wrapping cannot happen without generating an IRQ. I
would assume that ETE will then start again with an <async> data packet
first when the handler returns. Otherwise we might also have to insert
a similar barrier packet for the user space tool to reset. As trace data
should not get lost during an wrap event, ETE should complete the packet
after the handler returns, hence aux buffer should still have logically
contiguous stream of <synced trace data> to decode. I am not sure right
now, but will look into this.

- Anshuman

  reply	other threads:[~2020-11-23  3:40 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-10 12:44 Anshuman Khandual
2020-11-10 12:44 ` [RFC 01/11] arm64: Add TRBE definitions Anshuman Khandual
2020-11-10 12:45 ` [RFC 02/11] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
2020-11-12  9:21   ` Suzuki K Poulose
2020-11-12 10:37     ` Linu Cherian
2020-11-12 11:09       ` Suzuki K Poulose
2020-11-10 12:45 ` [RFC 03/11] coresight: Do not scan for graph if none is present Anshuman Khandual
2020-11-10 12:45 ` [RFC 04/11] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
2020-11-10 12:45 ` [RFC 05/11] coresight: ete: Add support for sysreg support Anshuman Khandual
2020-11-10 12:45 ` [RFC 06/11] coresight: ete: Detect ETE as one of the supported ETMs Anshuman Khandual
2020-11-14  5:36   ` Tingwei Zhang
2020-11-23  9:56     ` Suzuki K Poulose
2020-11-10 12:45 ` [RFC 07/11] coresight: sink: Add TRBE driver Anshuman Khandual
2020-11-12 10:13   ` Suzuki K Poulose
2020-11-25  5:25     ` Anshuman Khandual
2020-11-14  5:38   ` Tingwei Zhang
2020-11-23  3:51     ` Anshuman Khandual
2020-11-10 12:45 ` [RFC 08/11] coresight: etm-perf: Truncate the perf record if handle has no space Anshuman Khandual
2020-11-10 12:45 ` [RFC 09/11] coresight: etm-perf: Disable the path before capturing the trace data Anshuman Khandual
2020-11-12  9:27   ` Suzuki K Poulose
2020-11-23  6:08     ` Anshuman Khandual
2020-11-23 10:01       ` Suzuki K Poulose
2020-11-27 10:32   ` Suzuki K Poulose
2020-12-11 20:31     ` Mathieu Poirier
2020-12-14 10:00       ` Suzuki K Poulose
2020-11-10 12:45 ` [RFC 10/11] coresgith: etm-perf: Connect TRBE sink with ETE source Anshuman Khandual
2020-11-12  9:31   ` Suzuki K Poulose
2020-11-23  5:37     ` Anshuman Khandual
2020-12-11 21:31   ` Mathieu Poirier
2020-11-10 12:45 ` [RFC 11/11] dts: bindings: Document device tree binding for Arm TRBE Anshuman Khandual
2020-11-10 18:25 ` [RFC 00/11] arm64: coresight: Enable ETE and TRBE Mathieu Poirier
2020-11-14  5:17 ` Tingwei Zhang
2020-11-16 15:00   ` Mike Leach
2020-11-23  3:40     ` Anshuman Khandual [this message]
2020-11-23 12:30       ` Mike Leach
2020-11-23  2:43   ` Anshuman Khandual

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