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Fri, 06 Mar 2026 02:31:55 -0800 (PST) X-Received: by 2002:a05:6a21:2d44:b0:398:4b6a:90cc with SMTP id adf61e73a8af0-398590df8bcmr1886632637.70.1772793115260; Fri, 06 Mar 2026 02:31:55 -0800 (PST) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829a48dfc17sm1726877b3a.64.2026.03.06.02.31.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Mar 2026 02:31:54 -0800 (PST) Message-ID: Date: Fri, 6 Mar 2026 16:01:48 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/5] PCI: qcom: Power down PHY via PARF_PHY_CTRL before disabling rails/clocks To: Manivannan Sadhasivam Cc: Jingoo Han , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Will Deacon , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com References: <20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com> <20260217-d3cold-v2-4-89b322864043@oss.qualcomm.com> <313d2262-56e4-49b0-8455-2b46d0966976@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA2MDEwMCBTYWx0ZWRfXwXJBtv1E4QfA mCYcyom3V4CMB0vBYl2J7TZy2hCqBQWLhfGGOdAHKsWxFm4SPn/td+D+pdLc3xFHsAdwpjpVYUU ASBspBBPGXst47301kF1B5bwXue/mWn043GlDYxFMtxEPqTuQzpjwlCv1wZQn6AJagzMmRtv5Wi HknCFehleDTvNQuAW64cF0ZYJHSpZdGKmOTZjv0+BErgYKYBbml9anKhfEdSq3RDGpBvZBDGw4Z VFCcF3wgKMiLMJIDjHVwIXj54HX76GfkcKRpr9reCllPtYA98OI1h4btPrZeMuN4TM4ZsGHuifx NC/1iX0uoTw7aUpiXBKLZTrOzzmHMxYFsvQHdPy3Ccow3V5YotiL8X55FhJ89FAfKK8M/hQ4HLO TwcRXtWumjIQOFkFNJu9VGN6OIowxy4stdmO1xiZHDaN5Rs4r2oZcUm6+fRkYvBwMZWfZ0v76FF R6QudBgyZGxuXtjF5UQ== X-Proofpoint-ORIG-GUID: kwQN5zSVTW5yswS6DvUyQqVX2JMND6BO X-Proofpoint-GUID: kwQN5zSVTW5yswS6DvUyQqVX2JMND6BO X-Authority-Analysis: v=2.4 cv=T8uBjvKQ c=1 sm=1 tr=0 ts=69aaad1c cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=uIgEQj9WjdynuVTCvEgA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-06_03,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603060100 On 3/5/2026 2:48 PM, Manivannan Sadhasivam wrote: > On Thu, Mar 05, 2026 at 02:26:22PM +0530, Krishna Chaitanya Chundru wrote: >> >> On 3/5/2026 1:19 PM, Manivannan Sadhasivam wrote: >>> On Tue, Feb 17, 2026 at 04:49:09PM +0530, Krishna Chaitanya Chundru wrote: >>>> Some Qcom PCIe controller variants bring the PHY out of test power-down >>>> (PHY_TEST_PWR_DOWN) during init. When the link is later transitioned >>>> towards D3cold and the driver disables PCIe clocks and/or regulators >>>> without explicitly re-asserting PHY_TEST_PWR_DOWN, the PHY can remain >>>> partially powered, leading to avoidable power leakage. >>>> >>>> Update the init-path comments to reflect that PARF_PHY_CTRL is used to >>>> power the PHY on. Also, for controller revisions that enable PHY power >>>> in init (2.3.2, 2.3.3, 2.7.0 and 2.9.0), explicitly power the PHY down >>>> via PARF_PHY_CTRL in the deinit path before disabling clocks/regulators. >>>> >>>> This ensures the PHY is put into a defined low-power state prior to >>>> removing its supplies, preventing leakage when entering D3cold. >>>> >>>> Signed-off-by: Krishna Chaitanya Chundru >>>> --- >>>> drivers/pci/controller/dwc/pcie-qcom.c | 30 +++++++++++++++++++++++++++--- >>>> 1 file changed, 27 insertions(+), 3 deletions(-) >>>> >>>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >>>> index 2c4dc7134e006d3530a809f1bcc1a6488d4632ad..b02c19bbdf2ea5db252c2a0281a569bb3a0cc497 100644 >>>> --- a/drivers/pci/controller/dwc/pcie-qcom.c >>>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >>>> @@ -513,7 +513,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) >>>> u32 val; >>>> int ret; >>>> - /* enable PCIe clocks and resets */ >>>> + /* PHY power ON */ >>> This comment is confusing since we already have phy_power_on() API. What does >>> really happen in the 'test power down' case? >> QCOM PCIe controller wrapper has way to force the entire PHY into lowest >> power >> state by turning everything off, without this bit being cleared the phy will >> not be >> powered on even after phy_power_on(), we can think this as a kind of switch >> from the controller side to power on phy. >> > We never cared to set/clear this bit so far. So I'm assuming that if we simply > set it during init, it will not do any harm and allow the PHY to fully power > down itself when phy_power_off() is called? we are already doing set/clear of this bit, its not newly introduced one, I am updating the  comment  to correctly reflect hw behaviour. PHY power on looks little confusing I will update the commet to "Force PHY out of lowest mode". - Krishna Chaitanya. > - Mani >