From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5F9C037998F for ; Thu, 26 Feb 2026 11:52:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772106740; cv=none; b=Jgx0NQZs3arMMt7fP4sbcBHRYaDi5WAUafxKEYtcOHWh/rYGUopileYrtOEafpvvMxRHuWPpzafqu4kwQSxcxWRbTePxg8o+R+Sg09Br/35LbFW1vWU7jwXe7NIV4o9FI7xqJFzHp3rWO0UAv13JgYGscxKW/UMPf36P6wcIASE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772106740; c=relaxed/simple; bh=ib2RNDmtoLNfVYACoyVABvciUrTj7Tvua3pTRvLpNCM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ZopqZHHKc8DlWSSKFZ00+rlBJAXuBPoGUm7cvh+Ha6W/LnvuyVA6K1b71t1J4qFrJgDSVyN6q6fOZNn/LhyRBvBtqvK2M+rZDNIcIfzKf9cT3C5m3K1ldEXzuiRCdD5llPud9HwHuk97po2bRvyoUGnrXExlaF4VO+SIayxW1I0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 11D851516; Thu, 26 Feb 2026 03:52:11 -0800 (PST) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 416F83F62B; Thu, 26 Feb 2026 03:52:16 -0800 (PST) Date: Thu, 26 Feb 2026 11:52:07 +0000 From: Mark Rutland To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Ryan Roberts , linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64/mm: Describe 52 bits PA folding into TTBRx_EL1 Message-ID: References: <20260226101135.1915529-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260226101135.1915529-1-anshuman.khandual@arm.com> On Thu, Feb 26, 2026 at 10:11:35AM +0000, Anshuman Khandual wrote: > A 52 bits physical address gets stored in TTBR_BADDR_MASK_52 in a folded > manner. Shifting PA[51:0] right ward by '46' bits, aligns PA[51:48] into > TTBRx_EL1[5:2] which gets ORed for the final TTBRx_EL1 encoding. > > Define TTBR_BADDR_HIGH_52_PA_PIVOT which describes this inflection point, > where this right shift is done thus bringing some clarity to this 52 bits > PA address folding process in TTBRx_EL1. TBH, I don't think this is adding much as-is. The phys_to_ttbr macros are still inscrutable, even with '46' replaced with 'TTBR_BADDR_52_PA_PIVOT'. As last time, I think this would be better with explcit bit extraction/insertion, but I don't think it's necessary to actually change this unless it's enabling something else in future (which it doesn't seem to). i.e. I think we should leave this as-is. Mark. > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Ryan Roberts > Cc: Mark Rutland > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Anshuman Khandual > --- > This applies on v7.0-rc1 > > Earlier context can be found here. > > https://lore.kernel.org/linux-arm-kernel/aRb8ezhQd0c0jp9G@J2N7QTR9R3/ > > arch/arm64/include/asm/assembler.h | 2 +- > arch/arm64/include/asm/pgtable-hwdef.h | 14 ++++++++++++++ > arch/arm64/include/asm/pgtable.h | 3 ++- > 3 files changed, 17 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h > index d3d46e5f7188..a68002dd4c0e 100644 > --- a/arch/arm64/include/asm/assembler.h > +++ b/arch/arm64/include/asm/assembler.h > @@ -615,7 +615,7 @@ alternative_else_nop_endif > */ > .macro phys_to_ttbr, ttbr, phys > #ifdef CONFIG_ARM64_PA_BITS_52 > - orr \ttbr, \phys, \phys, lsr #46 > + orr \ttbr, \phys, \phys, lsr #TTBR_BADDR_52_PA_PIVOT > and \ttbr, \ttbr, #TTBR_BADDR_MASK_52 > #else > mov \ttbr, \phys > diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h > index d49180bb7cb3..21ca79f02a5d 100644 > --- a/arch/arm64/include/asm/pgtable-hwdef.h > +++ b/arch/arm64/include/asm/pgtable-hwdef.h > @@ -284,6 +284,20 @@ > * TTBR_ELx[1] is RES0 in this configuration. > */ > #define TTBR_BADDR_MASK_52 GENMASK_ULL(47, 2) > + > +/* > + * A 52 bit physical address gets stored in TTBR_BADDR_MASK_52 i.e > + * GENMASK(47, 2) in a folded manner. Shifting PA[51:0] right ward > + * by 46 bits aligns PA[51:48] into TTBRx_EL1[5:2] which gets ORed > + * subsequently for the final TTBRx_EL1 encoding. > + * > + * 47 5 2 0 > + * +----------------------------------------------+-----------+--+ > + * | PA[47:X] | PA[51:48] | | > + * +----------------------------------------------+-----------+--+ > + * > + */ > +#define TTBR_BADDR_52_PA_PIVOT (51 - 5) > #endif > > #ifdef CONFIG_ARM64_VA_BITS_52 > diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h > index b3e58735c49b..2f274c468d83 100644 > --- a/arch/arm64/include/asm/pgtable.h > +++ b/arch/arm64/include/asm/pgtable.h > @@ -1576,7 +1576,8 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf, > #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) > > #ifdef CONFIG_ARM64_PA_BITS_52 > -#define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) > +#define phys_to_ttbr(addr) (((addr) | ((addr) >> TTBR_BADDR_52_PA_PIVOT)) & \ > + TTBR_BADDR_MASK_52) > #else > #define phys_to_ttbr(addr) (addr) > #endif > -- > 2.30.2 >