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Mon, 02 Mar 2026 17:10:14 -0800 (PST) Date: Tue, 3 Mar 2026 09:09:46 +0800 From: Inochi Amaoto To: Yao Zi , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Siddharth Vadapalli , Hans Zhang <18255117159@163.com>, Kishon Vijay Abraham I , Chen Wang , Manikandan K Pillai , Christophe JAILLET , Inochi Amaoto , Han Gao Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports Message-ID: References: <20260227181925.52475-1-me@ziyao.cc> <20260227181925.52475-3-me@ziyao.cc> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Fri, Feb 27, 2026 at 06:24:12PM +0000, Yao Zi wrote: > On Fri, Feb 27, 2026 at 06:19:25PM +0000, Yao Zi wrote: > > Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM > > states for devicetree platforms") force enable ASPM on all device tree > > platform, the SG2042 root port breaks as it advertises L0s and L1 > > capabilities without supporting it. > > > > Provide a platform-specific initialization hook to override the L0s and > > L1 support advertised in LNKCAP register of SG2042 Root Ports, so it > > doesn't try to enable those states. > > > > Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042") > > Co-authored-by: Inochi Amaoto > > Oops, this should be Co-developed-by instead of Co-authored-by, sorry > for the silly mistake... > > > Signed-off-by: Inochi Amaoto > > Signed-off-by: Yao Zi > > Regards, > Yao Zi Thanks, and this patch is LGTM. With the tag fixed: Reviewed-by: Inochi Amaoto Regards, Inochi