From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-183.mta0.migadu.com (out-183.mta0.migadu.com [91.218.175.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA1473A1E77 for ; Wed, 4 Feb 2026 09:17:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.183 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770196653; cv=none; b=TKqTkXdZ2mcUtVBpjj+9ChzF+wplvjnS4LN5Zp8YiKM0EiGNrT0blvYNsFfM032KdmI/HSHLMW3Ca6a6wZOk4nnzoarMiEwWGPPYD/zdJnbdCX++9MUWQzSUXvzlTSY8Tbx3odaZgZDI+y4CU9MKm6m7Y8CuD6CIWhpxPC4i97g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770196653; c=relaxed/simple; bh=/VaXhL3gxMSF2HwhsH73iS3SoTKAcOpqpmie/UD8Wrg=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=BWdavJUFx+zmbS3Gv7sBG1eD340TxwdlULNPZPqEg6v6Lsd+dn1BdvYWazxEy/ndZHLJVwpC2zpNfMWWwPBzqYjvcmla+GbEZDWUZtPGCnwBf0tBfrZbwmX0AkyEmfZ6zoEifdIE7WakmIzwnS/IiNim2mCjHSvB54XYAfSsaQc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=cQ1myd0J; arc=none smtp.client-ip=91.218.175.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="cQ1myd0J" Message-ID: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1770196650; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4IM64raMxarRH21Rk3+wQo3JPtTbDyko4g9ZllcP0l4=; b=cQ1myd0Je2JXYaEJUEmGa3aP13WgndYrjdtGgnsuEw9PBYGbegG2HOz3JB+OeS9YforUNa /BfqNOHRZXXZV8XbQQJcBz2tOfNeZpHG/L6E13oPGE2P2fRlfYpIocrp2g0doyVp636mSP 8kAmvv2aRav2U86omWAUbftKt+EsBuY= Date: Wed, 4 Feb 2026 01:17:25 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH] drivers/perf: riscv: Keep the fixed counter counting To: cp0613@linux.alibaba.com, anup@brainfault.org, alex@ghiti.fr, pjw@kernel.org, guoren@kernel.org Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260131112440.2915-1-cp0613@linux.alibaba.com> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Atish Patra In-Reply-To: <20260131112440.2915-1-cp0613@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Migadu-Flow: FLOW_OUT On 1/31/26 3:24 AM, cp0613@linux.alibaba.com wrote: > From: Chen Pei > > The RISC-V SBI PMU driver disables all PMU counters during initialization > via pmu_sbi_stop_all. For fixed counters CYCLE, TIME and INSTRET, this is > unnecessary for the following two reasons: > > 1. Some kernel driver code may directly read CYCLE and INSTRET to perform > simple performance analysis. Is this for some debugging purpose to read the instret/cycle count at boot time or real use case for driver performance analysis ? If it is the latter, that will be problematic for various reasons such as context switching will lead to inaccurate numbers. > 2. In legacy mode, user space directly reads CYCLE and INSTRET. (echo 2 > > /proc/sys/kernel/perf_user_access) > > Therefore, We keep counting CYCLE, TIME and INSTRET. > > Signed-off-by: Chen Pei > --- > drivers/perf/riscv_pmu_sbi.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > index 7dd282da67ce..93aaab324443 100644 > --- a/drivers/perf/riscv_pmu_sbi.c > +++ b/drivers/perf/riscv_pmu_sbi.c > @@ -899,6 +899,9 @@ static int pmu_sbi_get_ctrinfo(int nctr, unsigned long *mask) > > static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu) > { > + /* We keep counting CYCLE, TIME and INSTRET. */ > + pmu->cmask &= ~0x7; > + This is incorrect. The cmask should be set based on the perf_user_access value. We should not continue counting the CYCLE/INSTRET when legacy mode is not set. if (sysctl_perf_user_access == SYSCTL_LEGACY) csr_write(CSR_SCOUNTEREN, 0x7); else csr_write(CSR_SCOUNTEREN, 0x2); > /* > * No need to check the error because we are disabling all the counters > * which may include counters that are not enabled yet.