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[94.134.107.193]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4366127c493sm361945625e9.28.2024.12.30.11.45.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Dec 2024 11:45:59 -0800 (PST) Message-ID: Date: Mon, 30 Dec 2024 21:45:49 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/6] arm64: dts: qcom: x1e80100: Add CAMCC block definition Content-Language: en-US To: Bryan O'Donoghue , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Mauro Carvalho Chehab , Bjorn Andersson , Michael Turquette , Stephen Boyd , Jagadeesh Kona , Konrad Dybcio Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-clk@vger.kernel.org References: <20241227-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v2-0-06fdd5a7d5bb@linaro.org> <20241227-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v2-4-06fdd5a7d5bb@linaro.org> From: Vladimir Zapolskiy In-Reply-To: <20241227-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v2-4-06fdd5a7d5bb@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Bryan. On 12/27/24 15:11, Bryan O'Donoghue wrote: > Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration > of previous CAMCC blocks with the exception of having two required > power-domains not just one. > > Signed-off-by: Bryan O'Donoghue > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index c18b99765c25c901b3d0a3fbaddc320c0a8c1716..5119cf64b461eb517e9306869ad0ec1b2cae629e 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. > */ > > +#include > #include > #include > #include It would be preferred to sort the list of includes in alphabetical order. > @@ -4647,6 +4648,22 @@ usb_1_ss1_dwc3_ss: endpoint { > }; > }; > > + camcc: clock-controller@ade0000 { > + compatible = "qcom,x1e80100-camcc"; > + reg = <0 0x0ade0000 0 0x20000>; > + clocks = <&gcc GCC_CAMERA_AHB_CLK>, > + <&bi_tcxo_div2>, > + <&bi_tcxo_ao_div2>, > + <&sleep_clk>; > + power-domains = <&rpmhpd RPMHPD_MXC>, > + <&rpmhpd RPMHPD_MMCX>; > + required-opps = <&rpmhpd_opp_low_svs>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + status = "disabled"; Please do not disable the clock controller, it was discussed in the past, that all clock controllers should be enabled by default. > + }; > + > mdss: display-subsystem@ae00000 { > compatible = "qcom,x1e80100-mdss"; > reg = <0 0x0ae00000 0 0x1000>; > -- Best wishes, Vladimir